Hadi Mardani Kamali

According to our database, Hadi Mardani Kamali authored at least 46 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation.

Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi

IEEE Trans. Very Large Scale Integr. Syst., February, 2024

Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration.

Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Trans. Inf. Forensics Secur., 2024

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.

Md Sami Ul Islam Sami, Tao Zhang, Amit Mazumder Shuvo, Md. Saad Ul Haque, Paul Calzada, Kimia Zamiri Azar, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Access, 2024

2023

Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.

Md Sami Ul Islam Sami, Hadi Mardani Kamali, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor

IEEE Des. Test, October, 2023

HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language.

Md Rafid Muttaki, Roshanak Mohammadivojdan, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach.

M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

IEEE Access, 2023

Security of Hardware Generators: Enabling Assurance in High-Level Synthesis.

Md Rafid Muttaki, Zahin Ibnat, Shang Shi, Hadi Mardani Kamali, Farimah Farahmandi

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking.

Mohammad Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Hadi Mardani Kamali

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis.

Zahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities.

Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

RTLock: IP Protection using Scan-Aware Logic Locking at RTL.

Md Rafid Muttaki, Shyvagata Saha, Hadi Mardani Kamali, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SheLL: Shrinking eFPGA Fabrics for Logic Locking.

Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction.

Rui Guo, M. Sazadur Rahman, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs.

Zahin Ibnat, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

SecHLS: Enabling Security Awareness in High-Level Synthesis.

Shang Shi, Nitin Pundir, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Advances in Logic Locking: Past, Present, and Prospects.

Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor

IACR Cryptol. ePrint Arch., 2022

Secure and Robust Key-Trapped Design-for-Security Architecture for Protecting Obfuscated Logic.

Hadi Mardani Kamali

IACR Cryptol. ePrint Arch., 2022

Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers.

Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

O'clock: lock the clock via clock-gating for SoC IP protection.

M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-Moneum, Mark M. Tehranipoor

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits.

Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan

IEEE Trans. Very Large Scale Integr. Syst., 2021

Deep Graph Learning for Circuit Deobfuscation.

Zhiqian Chen, Lei Zhang, Gaurav Kolhe, Hadi Mardani Kamali, Setareh Rafatirad, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Chang-Tien Lu, Liang Zhao

Frontiers Big Data, 2021

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains.

Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

IEEE Access, 2021

ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing.

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits.

Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain.

Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

IEEE Trans. Very Large Scale Integr. Syst., 2020

ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things.

Hadi Mardani Kamali, Kimia Zamiri Azar, Shervin Roshanisefat, Ashkan Vakil, Avesta Sasan

CoRR, 2020

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.

Shervin Roshanisefat, Hadi Mardani Kamali, Kimia Zamiri Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, Houman Homayoun, Avesta Sasan

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption.

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

InterLock: An Intercorrelated Logic and Routing Locking.

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures.

Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic.

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks.

Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

COMA: Communication and Obfuscation Management Architecture.

Kimia Zamiri Azar, Farnoud Farahmand, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, William Diehl, Kris Gaj, Avesta Sasan

Proceedings of the 22nd International Symposium on Research in Attacks, 2019

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers.

Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.

Gaurav Kolhe, Hadi Mardani Kamali, Miklesh Naicker, Tyler David Sheaves, Hamid Mahmoodi, Sai Manoj P. D., Houman Homayoun, Setareh Rafatirad, Avesta Sasan

Proceedings of the International Conference on Computer-Aided Design, 2019

Threats on Logic Locking: A Decade Later.

Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.

Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture.

Hadi Mardani Kamali, Kimia Zamiri Azar, Shaahin Hessabi

IEEE Trans. Computers, 2018

Using Multi-Core HW/SW Co-design Architecture for Accelerating K-means Clustering Algorithm.

Hadi Mardani Kamali

CoRR, 2018

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.

Hadi Mardani Kamali, Kimia Zamiri Azar, Kris Gaj, Houman Homayoun, Avesta Sasan

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers.

Hossein Farrokhbakht, Hadi Mardani Kamali, Natalie D. Enright Jerger, Shaahin Hessabi

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware.

Shervin Roshanisefat, Hadi Mardani Kamali, Avesta Sasan

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture.

Hadi Mardani Kamali, Avesta Sasan

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers.

Hossein Farrokhbakht, Hadi Mardani Kamali, Shaahin Hessabi

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

2016

A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard.

Hadi Mardani Kamali, Shaahin Hessabi

J. Circuits Syst. Comput., 2016

AdapNoC: A fast and flexible FPGA-based NoC simulator.

Hadi Mardani Kamali, Shaahin Hessabi

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016