Sri Harsha Choday

According to our database1, Sri Harsha Choday authored at least 7 papers between 2013 and 2018.

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Bibliography

2018
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning.
IEEE Micro, 2018

2016
Spin-Transfer Torque Memories: Devices, Circuits, and Systems.
Proc. IEEE, 2016

2014
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Spin Orbit Torque Based Electronic Neuron.
CoRR, 2014

Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Dual pillar spin-transfer torque MRAMs for low power applications.
ACM J. Emerg. Technol. Comput. Syst., 2013


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