Ashish Reddy Bommana

Orcid: 0000-0001-6321-6544

According to our database1, Ashish Reddy Bommana authored at least 13 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
COMET-3D: Compute-in-Memory-Based Transformer Accelerator With Optimized Pipeline and 3D Heterogeneous Integration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

PHANTOM: Power Hammering Attack and Countermeasure on Multi-Tenant ReRAM Compute-in-Memory Accelerators.
IEEE Trans. Inf. Forensics Secur., 2026

MoD-CiM: A Mixture-of-Defenses Framework Against Power-Hammering Attacks in Multi-Tenant Compute-in-Memory.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

WARP: Workload-Aware Reference Prediction for Reliable Multi-Bit FeFET Readout under Charge-Trapping Degradation.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

Noise-Agnostic One-Shot Training and Retraining for Robust DNN Inferencing on Analog Compute-in-Memory Systems.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
H3PIMAP: A Heterogeneity-Aware Multi-Objective DNN Mapping Framework on Electronic-Photonic Processing-in-Memory Architectures.
CoRR, March, 2025

Descriptive Language For 3D IC Die-to-Die Interconnect Repair For IEEE P3405 Standard.
Proceedings of the IEEE International Test Conference in Asia, 2025

Taming Sparse Giants: Deploying Mixture-of-Experts on 3D Heterogeneous Compute-in-Memory Systems.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

DEAR: Dependable 3D Architecture for Robust DNN Training.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

LiM Pruner: Efficient Pruning for Large Language-in-Memory Models.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2025

2024
SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2024

2023
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction.
ACM Trans. Design Autom. Electr. Syst., 2023

2022
A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022


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