Steffen Zeidler

Affiliations:
  • Brandenburg University of Technology, Germany (PhD 2013)


According to our database1, Steffen Zeidler authored at least 19 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Selective Fault Tolerance by Counting Gates with Controlling Value.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2016
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

An Early Stage Design Flow for Switching Noise Attenuation.
J. Circuits Syst. Comput., 2016

GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
A survey about testing asynchronous circuits.
Proceedings of the European Conference on Circuit Theory and Design, 2015

A Design Preconditioning Flow for Low-Noise Circuits.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2013
Enabling functional tests of asynchronous circuits using a test processor solution.
PhD thesis, 2013

Design of a low-power asynchronous elliptic curve cryptography coprocessor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Asynchronous circuit design: From basics to practical applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Overview on ATE Test and Debugging Methods for Asynchronous Circuits.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

Design of a Test Processor for Asynchronous Chip Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

On-line testing of bundled-data asynchronous handshake protocols.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009
Ultra low cost asynchronous handshake checker.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009


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