Matthew Fojtik

Orcid: 0000-0003-3138-9293

According to our database1, Matthew Fojtik authored at least 31 papers between 2010 and 2023.

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Bibliography

2023
Machine Learning and Algorithms: Let Us Team Up for EDA.
IEEE Des. Test, February, 2023

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.
Proceedings of the 2023 International Symposium on Physical Design, 2023

2021
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
CoRR, 2021

Simba: scaling deep-learning inference with chiplet-based architecture.
Commun. ACM, 2021

Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.
IEEE J. Solid State Circuits, 2020

2019
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.
Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation.
IEEE J. Solid State Circuits, 2016

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015
A Pausible Bisynchronous FIFO for GALS Systems.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2013
Centip3De: A 64-Core, 3D Stacked Near-Threshold System.
IEEE Micro, 2013

A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells.
IEEE J. Solid State Circuits, 2013

Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction.
IEEE J. Solid State Circuits, 2013

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS.
IEEE J. Solid State Circuits, 2013

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing.
Commun. ACM, 2013

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold.
Proceedings of the Symposium on VLSI Circuits, 2012

Bubble Razor: An architecture-independent approach to timing-error detection and correction.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Early detection of oxide breakdown through in situ degradation sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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