Sylvain Choisnet

According to our database, Sylvain Choisnet authored at least 7 papers between 2018 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor.

Benoît Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jérôme Chossat, Pascal Pierunek, Pascal Vivet, Sébastien Thuries

CoRR, June, 2025

SmartNMC: A 1Mb-200µW-20fps near-imager spatio-temporal inference hardware module.

William Guicquero, Nicolas Pelletier, Van Thien Nguyen, Jean-Philippe Noël, Manuel Pezzin, Marjorie Gary, Sylvain Choisnet

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS.

Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS.

Ivan Miro-Panades, Vincent Lorrain, Lilian Billod, Inna Kucher, Vincent Templier, Sylvain Choisnet, Nermine Ali, Baptiste Rossigneux, Olivier Bichler, Alexandre Valentian

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2020

A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition.

Arnaud Verdant, William Guicquero, Nicolas Royer, Guillaume Moritz, Sébastien Martin, Florent Lepin, Sylvain Choisnet, Fabrice Guellec, Benoît Deschamps, Sylvain Clerc, Jérôme Chossat

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.

Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.

Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018