Ivan Miro Panades

  • University Grenoble Alpes, CEA, Grenoble, France

According to our database1, Ivan Miro Panades authored at least 35 papers between 2006 and 2021.

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In proceedings 
PhD thesis 


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On csauthors.net:


Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

An optical clock receiver based on an injection locked ring oscillator featuring auto-calibration.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

3D advanced integration technology for heterogeneous systems.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
IEEE J. Solid State Circuits, 2014

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
Proceedings of the 19th IEEE European Test Symposium, 2014

Power management through DVFS and dynamic body biasing in FD-SOI circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

3D stacking for multi-core architectures: From WIDEIO to distributed caches.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.
Proceedings of the ESSCIRC 2013, 2013

3D integration for power-efficient computing.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive Stackable 3D Cache Architecture for Manycores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.
J. Low Power Electron., 2011

A 477mW NoC-based digital baseband for MIMO 4G SDR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures.
IEEE Des. Test Comput., 2008

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006