Romain Lemaire
Orcid: 0009-0003-5106-3925
According to our database1,
Romain Lemaire
authored at least 25 papers
between 2005 and 2023.
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Bibliography
2023
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration.
IEEE J. Solid State Circuits, 2023
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Analysis of the Influence of the Conduction Sub-Model Formulation on the Modeling of Laser-Induced Incandescence of Diesel Soot Aggregates.
Entropy, 2020
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
A Co-design Approach for Hardware Optimizations in Multicore Architectures Using MCAPI.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015
2013
Proceedings of the Design, Automation and Test in Europe, 2013
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
2011
Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip.
Proceedings of the NOCS 2011, 2011
2010
Design environment for the support of configurable Network Interfaces in NoC-based platforms.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.
Proceedings of the NOCS 2010, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
A Communication and configuration controller for NoC based reconfigurable data flow architecture.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
IEEE J. Solid State Circuits, 2008
2005
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proposition of a benchmark for evaluation of cores mapping onto NoC architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005