Sylvain Clerc

According to our database1, Sylvain Clerc authored at least 28 papers between 2008 and 2021.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2020

A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017
A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

30% static power improvement on ARM Cortex<sup>®</sup>-A53 using static biasing-anticipation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits.
Microelectron. Reliab., 2014

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.
IEEE J. Solid State Circuits, 2014


2013
Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.
Proceedings of the ESSCIRC 2013, 2013


2012
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance.
Proceedings of the 38th European Solid-State Circuit conference, 2012

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications.
ACM Trans. Design Autom. Electr. Syst., 2011

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
A 45nm single power supply SRAM supporting low voltage operation down to 0.6V.
Proceedings of the ESSCIRC 2008, 2008


  Loading...