Didier Lattard

According to our database1, Didier Lattard authored at least 33 papers between 1988 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

BISTs for post-bond test and electrical analysis of high density 3D interconnect defects.
Proceedings of the 23rd IEEE European Test Symposium, 2018

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
J. Solid-State Circuits, 2017

Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.
IEEE Design & Test, 2016

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

3D advanced integration technology for heterogeneous systems.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Computational load reduction by downsampling for energy-efficient digital baseband.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Non-coherent detection of M-ary orthogonal signals using Compressive Sensing.
Proceedings of the 9th International Symposium on Communication Systems, 2014

An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip.
Softw., Pract. Exper., 2012

A Stackable LTE Chip for Cost-effective 3D Systems.
IPSJ Trans. System LSI Design Methodology, 2012

A 3D reconfigurable platform for 4G telecom applications.
Proceedings of the Design, Automation and Test in Europe, 2011

An efficient hierarchical router for large 3D NoCs.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Flexible and distributed real-time control on a 4G telecom MPSoC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem.
Proceedings of the Design, Automation and Test in Europe, 2010

High level modelling and performance evaluation of address mapping in NAND flash memory.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Trends in complex SoC Design: From technology variability to multiprocessor architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Proposition of a benchmark for evaluation of cores mapping onto NoC architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

A Data Dependent Architecture Based on Seeded Region Growing Strategy for Advanced Morphological Operators.
Proceedings of the 3th International Symposium on Mathematical Morphology and its Applications to Image and Signal Processing, 1996

A VLSI implementation of parallel image reconstruction.
CVGIP: Graphical Model and Image Processing, 1991

Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction).
PhD thesis, 1989

An Integrated Asynchronous Cellular Array to Do Parallel Image Reconstruction.
Proceedings of IAPR Workshop on Computer Vision, 1988

An Integrated Highly Parallel Architecture for Image Reconstruction.
Proceedings of the Advances in Computer Graphics Hardware III (Eurographics'88 Workshop), 1988