Alexandre Valentian

According to our database1, Alexandre Valentian authored at least 39 papers between 2004 and 2022.

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Bibliography

2022
2022 roadmap on neuromorphic computing and engineering.
Neuromorph. Comput. Eng., 2022

Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022

2021
2021 Roadmap on Neuromorphic Computing and Engineering.
CoRR, 2021

Overcoming the Data Deluge Challenges with Greener Electronics.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Overcoming the Data Deluge Challenges with Greener Electronics.
Proceedings of the 47th ESSCIRC 2021, 2021

Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Fully-Integrated Spiking Neural Network Using SiOx-Based RRAM as Synaptic Device.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Spiking Neural Networks Hardware Implementations and Challenges: A Survey.
ACM J. Emerg. Technol. Comput. Syst., 2019

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural Networks.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Architecture exploration of a fixed point computation unit using precise timing spiking neurons.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI.
Microelectron. J., 2016

From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

UTBB FDSOI technology flexibility for ultra low power internet-of-things applications.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations.
J. Low Power Electron., 2014

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014


Shadow-scan design with low latency overhead and in-situ slack-time monitoring.
Proceedings of the 19th IEEE European Test Symposium, 2014

The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators.
Proceedings of the 2014 International Conference on Compilers, 2014

Advanced technologies for brain-inspired computing.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Comparing CMOS-Based and NEMS-Based Adiabatic Logic Circuits.
Proceedings of the Reversible Computation - 5th International Conference, 2013

An efficient metric of setup time for pulsed flip-flops based on output transition time.
Proceedings of 2013 International Conference on IC Design & Technology, 2013


2012
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Design challenges for nano-scale devices.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
Power Reduction of Asynchronous Logic Circuits Using Activity Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An Asynchronous Power Aware and Adaptive NoC Based Circuit.
IEEE J. Solid State Circuits, 2009

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability.
IEEE J. Solid State Circuits, 2008

A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs.
Proceedings of the ESSCIRC 2008, 2008

Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2004
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2004


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