Takahiro Kagami

According to our database, Takahiro Kagami authored at least 6 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Automatic Power Saving Method by Energy Aware Job Scheduler.

Hiroaki Imade, Takahiro Kagami, Tomohiro Otawa, Kouichi Hirai, Yoshio Sakaguchi, Naoyuki Fujita

Proceedings of the 2019 IEEE International Conference on Cluster Computing, 2019

2016

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano

IEEE Trans. Very Large Scale Integr. Syst., 2016

2014

Design of a low power NoC router using Marching Memory Through type.

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Low-latency wireless 3D NoCs via randomized shortcut chips.

Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power NoC router using the marching memory through type.

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2013

Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture.

Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013