Takeshi Okumoto

According to our database, Takeshi Okumoto authored at least 5 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.

Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

IEEE J. Solid State Circuits, 2015

2013

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits.

Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata

IEICE Trans. Electron., 2013

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.

Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2005

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits.

Makoto Nagata, Takeshi Okumoto, Kazuo Taki

IEEE J. Solid State Circuits, 2005

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits.

Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa

IEICE Trans. Electron., 2005