Tamer Ragheb

According to our database1, Tamer Ragheb authored at least 21 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2012
Calibration of propagation delay of flip-flops.
Proceedings of the IEEE 25th International SOC Conference, 2012

2009
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Numerical Design Optimization Methodology for Wideband and Multi-Band Inductively Degenerated Cascode CMOS Low Noise Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
On the feasibility of hardware implementation of sub-Nyquist random-sampling based analog-to-information conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Analytical modeling of common-gate low noise amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A fault-aware dynamic routing algorithm for on-chip networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design.
Microelectron. J., 2007

Implementing DSP Algorithms with On-Chip Networks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Variability-Aware Synthesis for Wideband Low Noise Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Theory and Implementation of an Analog-to-Information Converter using Random Demodulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Thermally robust clocking schemes for 3D integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers.
Proceedings of the 43rd Design Automation Conference, 2006


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