Andrew Marshall

According to our database1, Andrew Marshall authored at least 41 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2010, "For contributions to process development and design of integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Integrated Circuit Angular Displacement Sensor with On-chip Pinhole Aperture.
Sensors, 2020

A nociresponsive specific area of human somatosensory cortex within BA3a: BA3c?
NeuroImage, 2020

Whole-genome sequencing of patients with rare diseases in a national health system.
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Nat., 2020

MERAM: Non-Volatile Cache Memory Based on Magneto-Electric FETs.
CoRR, 2020

Adversarial Machine Learning-Industry Perspectives.
Proceedings of the 2020 IEEE Security and Privacy Workshops, 2020

Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Analog Performance Locking through Neural Network-Based Biasing.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

28nm STT-MRAM Array and Sense Amplifier.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

2018
Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Enhancing circuit operation using analog floating gates.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
The importance of benchmarking for charge-based and beyond CMOS devices.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Magneto-electric magnetic tunnel junction based analog circuit options.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Verilog - A compact model of a ME-MTJ based XNOR/NOR gate.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

2016
Image Analysis for Altimetry Waveform Selection Over Heterogeneous Inland Waters.
IEEE Geosci. Remote. Sens. Lett., 2016

Tutorial 4A: Supply voltage noise and mitigation for real world SoCs.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Tutorial 3B: The design challenges for self-powered wireless wearable ECG sensor SoC.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2014
Thoughts on Possible Future Charge-Based Technologies for Nano-Electronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Assessing the impact of derived behavior information on customer attrition in the financial service industry.
Eur. J. Oper. Res., 2014

T4A: System-on-chip design using Tri-gate technology.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Kodu alice and computer science unplugged: a model of effective introducing middle school students to computer science and computational thinking (abstract only).
Proceedings of the 45th ACM Technical Symposium on Computer Science Education, 2014

2013
Tutorial: The uncertain end to silicon.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2012
Calibration of propagation delay of flip-flops.
Proceedings of the IEEE 25th International SOC Conference, 2012

Invited talk: Noise and mismatch in sub 28nm silicon processes.
Proceedings of the IEEE 25th International SOC Conference, 2012

2010
Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
Mismatch and Noise in Modern IC Processes
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2009

Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Delivering Value Beyond Efficiency with Visualized XBRL.
Proceedings of the International Conference on Information Systems, 2009

2007
Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A merged MuGFET and planar SOI process.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A universal DC to logic performance correlation.
Proceedings of the 2007 IEEE International Test Conference, 2007

Advances in Multi-Gate MOSFET Circuit Design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Circuit design issues in multi-gate FET CMOS technologies.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Impact of negative bias temperature instability on digital circuit reliability.
Microelectron. Reliab., 2005

Workshop in Algorithmic Computer Music 2004 Music Center, University of California, Santa Cruz, USA; 25 June-9 July 2004.
Comput. Music. J., 2005

Dealing with Doctors: A Virtual Human for Non-team Interaction.
Proceedings of the 6th SIGdial Workshop on Discourse and Dialogue, 2005

2003
Evolution of user interaction: the case of agent adele.
Proceedings of the 8th International Conference on Intelligent User Interfaces, 2003

2002
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Quality Aspects of SOI Circuit Design (Tutorial Abstract).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

SOI SRAM design advances & considerations.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

PD-SOI and FD-SOI: a comparison of circuit performance.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

1995
Power IC Design for Testability.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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