Tatsunori Murotani

According to our database1, Tatsunori Murotani authored at least 6 papers between 1990 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.
IEEE J. Solid State Circuits, 2000

1997
A four-level storage 4-Gb DRAM.
IEEE J. Solid State Circuits, 1997

1995
A 1-Gb DRAM for file applications.
IEEE J. Solid State Circuits, November, 1995

1993
A 30-ns 256-Mb DRAM with a multidivided array structure.
IEEE J. Solid State Circuits, November, 1993

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992

1990
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM.
IEEE J. Solid State Circuits, August, 1990


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