Thomas J. Bucelot

According to our database, Thomas J. Bucelot authored at least 9 papers between 1991 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Resonant clock mega-mesh for the IBM z13^TM.

David Shan, Phillip J. Restle, Doug Malone, Robert A. Groves, Eric Lai, Michael Koch, Jason Hibbeler, Yong Kim, Christos Vezyrtzis, Jan Feder, David Hogenmiller, Thomas J. Bucelot

Proceedings of the Symposium on VLSI Circuits, 2015

2014

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8^TM microprocessor.

Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

On-chip circuit for measuring multi-GHz clock signal waveforms.

Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2008

A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor.

Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.

Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2003

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.

Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu

IEEE J. Solid State Circuits, 2003

2002

Infrastructure requirements for a large-scale, multi-site VLSI development project.

Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins

IBM J. Res. Dev., 2002

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design.

Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1991

A 4-Mb low-temperature DRAM.

Walter H. Henkels, Duen-Shun Wen, Rick L. Mohler, Robert L. Franch, Thomas J. Bucelot, Christopher W. Long, John A. Bracchitta, W. J. Cote, Gary B. Bronner, Yuan Taur, Robert H. Dennard

IEEE J. Solid State Circuits, November, 1991