Phillip J. Restle
Orcid: 0000-0002-3124-4265Affiliations:
- IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
According to our database1,
Phillip J. Restle
authored at least 47 papers
between 1997 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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Bibliography
2023
IEEE J. Solid State Circuits, 2023
2022
Deterministic Frequency Boost and Voltage Enhancements on the POWER10<sup>TM</sup> Processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2019
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems.
IEEE J. Solid State Circuits, 2019
2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!).
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
2014
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Optimization and modeling of resonant clocking inductors for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the Symposium on VLSI Circuits, 2012
2011
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the 2009 International Symposium on Physical Design, 2009
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
IBM J. Res. Dev., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005
2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.
IEEE J. Solid State Circuits, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Proceedings of the 38th Design Automation Conference, 2001
1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor.
IEEE J. Solid State Circuits, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
1997
IEEE J. Solid State Circuits, 1997