Joshua Friedrich

According to our database1, Joshua Friedrich authored at least 23 papers between 2004 and 2018.

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Bibliography

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

2017
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

2014
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
IBM POWER7+ design for higher frequency at fixed power.
IBM J. Res. Dev., 2013

2012
Power/performance optimization of many-core processor SoCs.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Optical PCB interconnects, Niche or mainstream?
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Session 3 overview: Processors: High performance digital subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits, 2011

Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

2010
The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

POWER7<sup>TM</sup> local clocking and clocked storage elements.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
The opportunity cost of low power design: a case study in circuit tuning.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Design and Implementation of the POWER6 Microprocessor.
IEEE J. Solid State Circuits, 2008

On-chip Timing Uncertainty Measurements on IBM Microprocessors.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.
IBM J. Res. Dev., 2007

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007


2004


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