David W. Boerstler

According to our database, David W. Boerstler authored at least 15 papers between 1992 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2015

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban

IEEE J. Solid State Circuits, 2015

2014

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8^TM microprocessor.

Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai

IBM J. Res. Dev., 2013

On-chip circuit for measuring multi-GHz clock signal waveforms.

Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2007

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology.

Fadi H. Gebara, Jeremy D. Schaub, Tuyet Nguyen, Jarom Peña, Ivan Vo, David Boerstler, Kevin J. Nowka

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Implementation of the 65nm Cell Broadband Engine.

Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.

Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa

IEEE J. Solid State Circuits, 2006

A Circuit for Reducing Large Transient Current Effects on Processor Power Grids.

Eskinder Hailu, David W. Boerstler, Kazuhiko Miki, Jieming Qi, Michael Wang, Mack W. Riley

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A new test and characterization scheme for 10+ GHz low jitter wide band PLL.

Kazuhiko Miki, David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill, Yuichi Goto

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2001

A clock distribution network for microprocessors.

Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie

IEEE J. Solid State Circuits, 2001

2000

"Timing closure by design, " a high frequency microprocessor design methodology.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia

Proceedings of the 37th Conference on Design Automation, 2000

1999

A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz.

David W. Boerstler

IEEE J. Solid State Circuits, 1999

1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.

Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

IEEE J. Solid State Circuits, 1998

Design methodology for a 1.0 GHz microprocessor.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1992

IBM Enterprise Systems multimode fiber optic technology.

Nancy R. Aulet, David W. Boerstler, George DeMario, Frank D. Ferraiolo, Curtis E. Hayward, Charles D. Heath, Allen L. Huffman, William R. Kelly, Gerald W. Peterson, Daniel J. Stigliani Jr.

IBM J. Res. Dev., 1992