Thomas Marconi

According to our database1, Thomas Marconi authored at least 21 papers between 2007 and 2017.

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Bibliography

2017
Low cost multi-error correction for 3D polyhedral memories.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

LDPC-Based Adaptive Multi-Error Correction for 3D Memories.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2015
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays.
Comput. Electr. Eng., 2014

Transmission Channel Noise Aware Energy Effective LDPC Decoding.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Towards energy effective LDPC decoding by exploiting channel noise variability.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

2013
Implementation of core coalition on FPGAs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012
Online scheduling for multi-core shared reconfigurable fabric.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Efficient Runtime Management of Reconfigurable Hardware Resources.
PhD thesis, 2011

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A novel HDL coding style to reduce power consumption for reconfigurable devices.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Flexible pipelining design for recursive variable expansion.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
A self-adaptive on-line task placement algorithm for partially reconfigurable systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

An efficient algorithm for free resources management on the FPGA.
Proceedings of the Design, Automation and Test in Europe, 2008

Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007


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