Todor P. Stefanov

According to our database1, Todor P. Stefanov authored at least 84 papers between 2001 and 2019.

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Bibliography

2019
Fault-Tolerant Nanosatellite Computing on a Budget.
CoRR, 2019

Ensemble of Convolutional Neural Networks for P300 Speller in Brain Computer Interface.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Text and Time Series, 2019

A Dynamic Bypass Approach to Realize Power Efficient Network-on-Chip.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

SLES: A Novel CNN-based Method for Sensor Reduction in P300 Speller.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019

Enabling Cognitive Autonomy on Small Drones by Efficient On-Board Embedded Computing: An ORB-SLAM2 Case Study.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoC.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Hard Real-Time Scheduling of Streaming Applications Modeled as Cyclic CSDF Graphs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Surf-Bless: A Confined-interference Routing for Energy-Efficient Communication in NoCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Optimization and deployment of CNNs at the edge: the ALOHA experience.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Resource Optimization for Real-Time Streaming Applications Using Task Replication.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Scheduling Analysis of Imprecise Mixed-Criticality Real-Time Tasks.
IEEE Trans. Computers, 2018

Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks.
IEEE Trans. Computers, 2018

A Simple Convolutional Neural Network for Accurate P300 Detection and Character Spelling in Brain Computer Interface.
Proceedings of the Twenty-Seventh International Joint Conference on Artificial Intelligence, 2018

ALOHA: an architectural-aware framework for deep learning at the edge.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

Dynamic Fault Tolerance Through Resource Pooling.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Preliminary Performance Estimations and Benchmark Results for a Software-based Fault-Tolerance Approach aboard Miniaturized Satellite Computers.
CoRR, 2017

Energy-efficient scheduling of throughput-constrained streaming applications by periodic mode switching.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
On the Improved Hard Real-Time Scheduling of Cyclo-Static Dataflow.
ACM Trans. Embedded Comput. Syst., 2016

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Energy efficient semi-partitioned scheduling for embedded multiprocessor streaming systems.
Design Autom. for Emb. Sys., 2016

EDF-VD Scheduling of Mixed-Criticality Systems with Degraded Quality Guarantees.
Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

Energy-Efficient Scheduling of Real-Time Tasks on Heterogeneous Multicores Using Task Splitting.
Proceedings of the 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2016

Exploiting resource-constrained parallelism in hard real-time streaming applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Energy-efficient mapping of real-time applications on heterogeneous MPSoCs using task replication.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Parametrized system level design: Real-time X-Ray image processing case study.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Message from the Chairs.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Energy-efficient mapping of real-time streaming applications on cluster heterogeneous MPSoCs.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Improved hard real-time scheduling of CSDF-modeled streaming applications.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
Editorial: Special Section on ESTIMedia'13.
ACM Trans. Embedded Comput. Syst., 2014

Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Resource optimization for CSDF-modeled streaming applications with latency constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

System-level scheduling of real-time streaming applications using a semi-partitioned approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Mapping of streaming applications considering alternative application specifications.
ACM Trans. Embedded Comput. Syst., 2013

Automated generation of polyhedral process networks from affine nested-loop programs with dynamic loop bounds.
ACM Trans. Embedded Comput. Syst., 2013

A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

On the hard-real-time scheduling of embedded streaming applications.
Design Autom. for Emb. Sys., 2013

An accurate energy model for streaming applications mapped on MPSoC platforms.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Message from the chairs.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.
VLSI Design, 2012

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.
IET Computers & Digital Techniques, 2012

Mapping of streaming applications considering alternative application specifications (Extended abstract).
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A methodology for automated design of hard-real-time embedded streaming systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Managing latency in embedded streaming applications under hard-real-time scheduling.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Automatic derivation of polyhedral process networks from while-loop affine programs.
Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

Hard-real-time scheduling of data-dependent tasks in embedded streaming applications.
Proceedings of the 11th International Conference on Embedded Software, 2011

Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-Chip.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

Modeling adaptive streaming applications with parameterized polyhedral process networks.
Proceedings of the 48th Design Automation Conference, 2011

IP-XACT extensions for Reconfigurable Computing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Design Trade-offs in Customized On-chip Crossbar Schedulers.
Signal Processing Systems, 2010

Identifying communication models in Process Networks derived from Weakly Dynamic Programs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Translating affine nested-loop programs with dynamic loop bounds into Polyhedral Process Networks.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Combining process splitting and merging transformations for Polyhedral Process Networks.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Throughput modeling to evaluate process merging transformations in polyhedral process networks.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Optimal Loop Unrolling and Shifting for Reconfigurable Architectures.
TRETS, 2009

Electronic System-Level Synthesis Methodologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Flexible pipelining design for recursive variable expansion.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

On compile-time evaluation of process partitioning transformations for Kahn process networks.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Systematic and Automated Multiprocessor System Design, Programming, and Implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM.
EURASIP J. Emb. Sys., 2008

System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Loop unrolling and shifting for reconfigurable architectures.
Proceedings of the FPL 2008, 2008

Daedalus: toward composable multimedia MP-SoC design.
Proceedings of the 45th Design Automation Conference, 2008

2007
pn: A Tool for Improved Derivation of Process Networks.
EURASIP J. Emb. Sys., 2007

Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.
Proceedings of the FPL 2007, 2007

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Customizing Reconfigurable On-Chip Crossbar Scheduler.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Systematic Customization of On-Chip Crossbar Interconnects.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Multi-processor system design with ESPAM.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
System Design Using Kahn Process Networks: The Compaan/Laura Approach.
Proceedings of the 2004 Design, 2004

2003
Laura: Leiden Architecture Research and Exploration Tool.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Deriving process networks from weakly dynamic applications in system-level design.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Algorithmic transformation techniques for efficient exploration of alternative application instances.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
System Level Design with Spade: an M-JPEG Case Study.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001


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