Tiago Reimann

Orcid: 0000-0002-3730-0213

According to our database1, Tiago Reimann authored at least 11 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2016
Challenges of cell selection algorithms in industrial high performance microprocessor designs.
Integr., 2016

Cell Selection for High-Performance Designs in an Industrial Design Flow.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

2015
Gate sizing and threshold voltage assignment for high performance microprocessor designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
GR-PA: A cost pre-allocation model for global routing.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010
Routing algorithms performance in different routing scopes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
On the accuracy of Elmore-based Delay Models.
Proceedings of the 16th IEEE International Conference on Electronics, 2009


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