Gracieli Posser

According to our database1, Gracieli Posser authored at least 19 papers between 2010 and 2022.

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Bibliography

2022
Challenges and Approaches in VLSI Routing.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2019
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2018
ISPD 2018 Initial Detailed Routing Contest and Benchmarks.
Proceedings of the 2018 International Symposium on Physical Design, 2018

2016
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reducing the number of transistors with gate clustering.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

FinFET cells with different transistor sizing techniques against PVT variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Electromigration aware circuits by using special signal non-default routing rules.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Process variability in FinFET standard cells with different transistor sizing techniques.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Impact on performance, power, area and wirelength using electromigration-aware cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Analyzing the electromigration effects on different metal layers and different wire lengths.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A systematic approach for analyzing and optimizing cell-internal signal electromigration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Transistor sizing and gate sizing using geometric programming considering delay minimization.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
Gate Sizing Minimizing Delay and Area.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
A study on layout quality of automatic generated cells.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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