Guilherme Flach

According to our database, Guilherme Flach authored at least 21 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Rsyn: An Extensible Physical Synthesis Framework.

Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016

Leakage current analysis in static CMOS logic gates for a transistor network design approach.

Jorge L. Tonfat, Guilherme Flach, Ricardo Reis

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Improving placement algorithms by using visualization tools.

Mateus Fogaça, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Routing-Aware Incremental Timing-Driven Placement.

Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.

Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Quadratic timing objectives for incremental timing-driven placement optimization.

Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

An Incremental Timing-Driven flow using quadratic formulation for detailed placement.

Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Jezz: An Effective Legalization Algorithm for Minimum Displacement.

Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

An analytical timing-driven algorithm for detailed placement.

Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.

Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A tool to simulate optical lithography in nanoCMOs.

Tania Mara Ferla, Guilherme Flach, Ricardo Reis

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2013

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.

Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.

Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

High-performance clock mesh optimization.

Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis

ACM Trans. Design Autom. Electr. Syst., 2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Quadratic placement with single-iteration linear system solver.

Guilherme Flach, Marcelo O. Johann, Ricardo Reis

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Gate Sizing Minimizing Delay and Area.

Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

A Mesh-Buffer Displacement Optimization Strategy.

Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2007

Cell placement on graphics processing units.

Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.

Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.

Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006