Guilherme Flach

According to our database1, Guilherme Flach authored at least 21 papers between 2006 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Rsyn: An Extensible Physical Synthesis Framework.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
Leakage current analysis in static CMOS logic gates for a transistor network design approach.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Improving placement algorithms by using visualization tools.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Routing-Aware Incremental Timing-Driven Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Quadratic timing objectives for incremental timing-driven placement optimization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Jezz: An Effective Legalization Algorithm for Minimum Displacement.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

An analytical timing-driven algorithm for detailed placement.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A tool to simulate optical lithography in nanoCMOs.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2013
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
High-performance clock mesh optimization.
ACM Trans. Design Autom. Electr. Syst., 2012

Transistor sizing and gate sizing using geometric programming considering delay minimization.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
Quadratic placement with single-iteration linear system solver.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Gate Sizing Minimizing Delay and Area.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
A Mesh-Buffer Displacement Optimization Strategy.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2007
Cell placement on graphics processing units.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006


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