Hideaki Anbutsu

According to our database, Hideaki Anbutsu authored at least 4 papers between 1998 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners.

Masazumi Marutani, Hideaki Anbutsu, Masafumi Kondo, Noriaki Shirai, Hiroshi Yamazaki, Yuu Watanabe

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

A CMOS multichannel 10-Gb/s transceiver.

Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

IEEE J. Solid State Circuits, 2003

1999

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism.

Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada

IEEE J. Solid State Circuits, 1999

1998

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications.

Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai

IEEE J. Solid State Circuits, 1998