Hiromasa Takahashi

According to our database1, Hiromasa Takahashi authored at least 9 papers between 1990 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Can players avoid the tragedy of the commons in a joint debt game?
Int. J. Game Theory, 2020

2011
A vector coprocessor architecture for embedded systems.
Proceedings of the International SoC Design Conference, 2011

2010
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.
IEEE J. Solid State Circuits, 2010

2008
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.
IEEE J. Solid State Circuits, 2008

2007
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2004
Autonomous decentralized control for formation of multiple mobile robots considering ability of robot.
IEEE Trans. Ind. Electron., 2004

1993
The μVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation.
IEEE Micro, 1993

1990
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990


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