François Marc

According to our database1, François Marc authored at least 26 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020

2019
Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst., 2018

Influence of temperature of storage, write and read operations on multiple level cells NAND flash memories.
Microelectron. Reliab., 2018

2017
Proceedings of the 28th European Symposium on the reliability of electron devices, failure physics and analysis.
Microelectron. Reliab., 2017

2016
FPGA LUT delay degradation due to HCI: Experiment and simulation results.
Microelectron. Reliab., 2016

Modelling delay degradation due to NBTI in FPGA Look-up tables.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Design and implementation of a low cost test bench to assess the reliability of FPGA.
Microelectron. Reliab., 2015

Editorial.
Microelectron. Reliab., 2015

2013
Editorial.
Microelectron. Reliab., 2013

On the Simulation of HCI-Induced Variations of IC Timings at High Level.
J. Electron. Test., 2013

2012
Impact of Power Consumption and Temperature on Processor Lifetime Reliability.
J. Low Power Electron., 2012

Relation between HCI-induced performance degradation and applications in a RISC processor.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Advancements on reliability-aware analog circuit design.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses.
Microelectron. Reliab., 2011

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design.
Microelectron. Reliab., 2011

2010
Preliminary results of storage accelerated aging test on InP/InGaAs DHBT.
Microelectron. Reliab., 2010

Thermal aging model of InP/InGaAs/InP DHBT.
Microelectron. Reliab., 2010

High Level Power and Energy Exploration Using ArchC.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009
Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror.
Microelectron. Reliab., 2009

2007
Statistical analysis during the reliability simulation.
Microelectron. Reliab., 2007

2006
Multi-level Modeling of Hot Carrier Injection for Reliability.
Proceedings of the Forum on specification and Design Languages, 2006

2004
Reliability of Low-Cost PCB Interconnections for Telecommunication Applications.
Microelectron. Reliab., 2004

2003
Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study.
Microelectron. Reliab., 2003

Reliability simulation of electronic circuits with VHDL-AMS.
Proceedings of the Forum on specification and Design Languages, 2003

2002
Contribution to ageing simulation of complex analogue circuit using VHDL-AMS behavioural modelling language.
Microelectron. Reliab., 2002


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