Olivier Héron

According to our database, Olivier Héron authored at least 25 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Towards Privacy-first Manufacturing Data Exchange Platform.

Thanh-Hai Nguyen, Olivier Héron, Olivier Riou

Proceedings of the 12th International Symposium on Information and Communication Technology, 2023

2019

Estimation of oxide breakdown effects by fault injection.

Chiara Sandionigi, Olivier Héron

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2017

Early estimation of aging in the design flow of integrated circuits through a programmable hardware module.

Chiara Sandionigi, Maurício Altieri, Olivier Héron

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

Tracking BTI and HCI effects at circuit-level in adaptive systems.

Maurício Altieri, Suzanne Lesecq, Edith Beigné, Olivier Héron, Diego Puschini

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Fine-grain analysis of the parameters involved in aging of digital circuits.

Boukary Ouattara, Olivier Héron, Chiara Sandionigi

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

2015

Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.

Maurício Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Workload-dependent BTI analysis in a processor core at high level.

Olivier Héron, Chiara Sandionigi, E. Piriou, Safa Mbarek, Vincent Huard

Proceedings of the IEEE International Reliability Physics Symposium, 2015

Identifying aging-aware representative paths in processors.

Chiara Sandionigi, Olivier Héron

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2013

On the Simulation of HCI-Induced Variations of IC Timings at High Level.

Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc

J. Electron. Test., 2013

When processors get old: Evaluation of BTI and HCI effects on performance and reliability.

Chiara Sandionigi, Olivier Héron, Clement Bertolini, Raphaël David

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Impact of Power Consumption and Temperature on Processor Lifetime Reliability.

Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc

J. Low Power Electron., 2012

Relation between HCI-induced performance degradation and applications in a RISC processor.

Clement Bertolini, Olivier Héron, Nicolas Ventroux, François Marc

Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

2011

Impact of the application activity on intermittent faults in embedded systems.

Julien Guilhemsang, Olivier Héron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A Lightweight API for an Adaptive Software Fault Tolerance Using POSIX-Thread Replication.

Abdellah Kouadri, Olivier Héron, Romain Montagné

Proceedings of the ARCS 2011, 2011

Impact of power management on temperature and reliability evolution for an embedded many-core architecture.

M. Alexandre Carbon, Olivier Héron, Karim Ben Chehida, Raphaël David

Proceedings of the ARCS 2011, 2011

2010

High Level Power and Energy Exploration Using ArchC.

Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc

Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologies.

Olivier Héron, Julien Guilhemsang, Nicolas Ventroux, Alain Giulieri

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2006

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

J. Electron. Test., 2006

2005

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

J. Electron. Test., 2005

On the Reliability Evaluation of SRAM-Based FPGA Designs.

Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 9th European Test Symposium, 2004

High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Defect Analysis for Delay-Fault BIST in FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Requirements for delay testing of look-up tables in SRAM-based FPGAs.

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell

Proceedings of the 8th European Test Workshop, 2003