Shihui Yin

According to our database1, Shihui Yin authored at least 36 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Energy-Efficient Circuit and Architecture Designs for Intelligent Systems.
PhD thesis, 2020

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks.
IEEE J. Solid State Circuits, 2020

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020

C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism.
IEEE J. Solid State Circuits, 2020

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020

Deep Neural Network Training Accelerator Designs in ASIC and FPGA.
Proceedings of the International SoC Design Conference, 2020

Efficient and Modularized Training on FPGA for Real-time Applications.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019

A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019

Inference engine benchmarking across technological platforms from CMOS to RRAM.
Proceedings of the International Symposium on Memory Systems, 2019

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019

XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
Environment-Adaptable Fast Multi-Resolution (EAF-MR) optimization in large-scale RF-FPGA systems.
EURASIP J. Wirel. Commun. Netw., 2018

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Efficient programming of reconfigurable radio frequency (RF) systems.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Designing ECG-based physical unclonable function for security of wearable devices.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers.
Proceedings of the 2015 IEEE Global Communications Conference, 2015

Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015


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