Peichen Pan

According to our database1, Peichen Pan authored at least 28 papers between 1992 and 2017.

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Bibliography

2017
Comparative analyses of structural features and scaffold diversity for purchasable compound libraries.
J. Cheminformatics, 2017

2016
Sequential Circuit Technology Mapping.
Encyclopedia of Algorithms, 2016

Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Source-to-Source Optimization for HLS.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Identification and Preliminary SAR Analysis of Novel Type-I Inhibitors of TIE-2 via Structure-Based Virtual Screening and Biological Evaluation in in vitro Models.
Journal of Chemical Information and Modeling, 2015

2014
Assessing an Ensemble Docking-Based Virtual Screening Strategy for Kinase Targets by Considering Protein Flexibility.
Journal of Chemical Information and Modeling, 2014

2013
Development and Evaluation of an Integrated Virtual Screening Strategy by Combining Molecular Docking and Pharmacophore Searching Based on Multiple Protein Structures.
Journal of Chemical Information and Modeling, 2013

Molecular Principle of Topotecan Resistance by Topoisomerase I Mutations through Molecular Modeling Approaches.
Journal of Chemical Information and Modeling, 2013

2008
Sequential Circuit Technology Mapping.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

2006
FPGA Design Automation: A Survey.
Foundations and Trends in Electronic Design Automation, 2006

2002
Monotone bipartitioning problem in a planar point set with applications to VLSI.
ACM Trans. Design Autom. Electr. Syst., 2002

1999
Partial Scan with Preselected Scan Signals.
IEEE Trans. Computers, 1999

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Optimal Retiming for Initial State Computation.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Performance-Driven Integration of Retiming and Resynthesis.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Optimal clock period FPGA technology mapping for sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 1998

Optimal clock period clustering for sequential circuits with retiming.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Low power logic synthesis under a general delay model.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
Optimal Graph Constraint Reduction for Symbolic Layout Compaction.
Algorithmica, 1997

Continuous Retiming: Algorithms and Applications.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Area Minimization for Hierarchical Floorplans.
Algorithmica, 1996

Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Desensitization for Power Reduction in Sequential Circuits.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Area minimization for floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Partial Scan with Pre-selected Scan Signals.
Proceedings of the 32st Conference on Design Automation, 1995

1992
Area minimization for general floorplans.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992


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