René Schüffny

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A pulse communication flow ready for accelerated neuromorphic experiments.

[BibT_eX]

[DOI]

Bernhard Vogginger

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A compact on-chip IR-drop measurement system in 28 nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Configurable pulse routing architecture for accelerated multi-node neuromorphic systems.

[BibT_eX]

[DOI]

Bernhard Vogginger

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

An energy efficient multi-bit TSV transmitter using capacitive coupling.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Integrated circuits processing chemical information: Prospects and challenges.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Neural Schematics as a unified formal graphical representation of large-scale Neural Network Structures.

[BibT_eX]

[DOI]

Matthias Ehrlich

Frontiers Neuroinformatics, 2013

Hybrid incremental-ΣΔ-ADC for ambient light sensing applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Live demonstration: Multiple-timescale plasticity in a neuromorphic system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A model based comparison of BiFeO3 device applicability in neuromorphic hardware.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A location-independent direct link neuromorphic interface.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Rapid prototyping of higher order incremental ΣΔ-ADC topologies and NTFs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Analysis of a charge redistribution SAR ADC with partially thermometer coded DAC.

[BibT_eX]

[DOI]

Stefan Hänzsche

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Behavioral model of a continuous current integrator with time discrete feedback and sampling.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks.

[BibT_eX]

[DOI]

Stephan Henker

J. Comput. Neurosci., 2012

A 32 GBit/s communication SoC for a waferscale neuromorphic system.

[BibT_eX]

[DOI]

Integr., 2012

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2012

Developing structural constraints on connectivity for biologically embedded neural networks.

[BibT_eX]

[DOI]

Biol. Cybern., 2012

Waveform Driven Plasticity in BiFeO3 Memristive Devices: Model and Implementation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 25: 26th Annual Conference on Neural Information Processing Systems 2012. Proceedings of a meeting held December 3-6, 2012

A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.

[BibT_eX]

[DOI]

Marc-Olivier Schwartz

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 14 bit self-calibrating charge redistribution SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Incremental-ΣΔ-ADCs with dynamic conversion length adaption.

[BibT_eX]

[DOI]

Johannes Uhlig

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Long-term pulse stimulation and recording in an accelerated neuromorphic system.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 2011

A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.

[BibT_eX]

[DOI]

Biol. Cybern., 2011

An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs.

[BibT_eX]

[DOI]

Johannes Uhlig

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on System on Chip, 2011

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Synapse dynamics in CMOS derived from a model of neurotransmitter release.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Efficient compensation of delay variations in high-speed network-on-chip data links.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

A low-power cell-based-design multi-port register file in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Replicating experimental spike and rate based neural learning in CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Wide swing signal amplification by SC voltage doubling.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A critique of BCM behavior verification for STDP-type plasticity models.

[BibT_eX]

[DOI]

Proceedings of the 18th European Symposium on Artificial Neural Networks, 2010

GMPath - A Path Language for Navigation, Information Query and Modification of Data Graphs.

[BibT_eX]

Karsten Wendt

Matthias Ehrlich

Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2010

A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System.

[BibT_eX]

Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2010

2009

A novel ADPLL design using successive approximation frequency control.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Transient responses of activity-dependent synapses to modulated pulse trains.

[BibT_eX]

[DOI]

Neurocomputing, 2009

On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz.

[BibT_eX]

[DOI]

Comput. Intell. Neurosci., 2009

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Current conveyor based amplifier and adaptive buffer for use in an analog frontend.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

On the routing complexity of neural network models - Rent's Rule revisited.

[BibT_eX]

[DOI]

Proceedings of the 17th European Symposium on Artificial Neural Networks, 2009

2008

BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

2007

Gabor-Like Image Filtering Using a Neural Microcircuit.

[BibT_eX]

[DOI]

Arne Heittmann

IEEE Trans. Neural Networks, 2007

Neighborhood Rank Order Coding for Robust Texture Analysis and Feature Extraction.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hybrid Intelligent Systems, 2007

2005

Applying Spiking Neural Nets to Noise Shaping.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

2004

Design and evaluation of current-mode image sensors in CMOS-technology.

[BibT_eX]

[DOI]

Matthias Tänzer

Achim Graupner

IEEE Trans. Circuits Syst. II Express Briefs, 2004

An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation.

[BibT_eX]

[DOI]

Proceedings of the Image Processing: Algorithms and Systems III, 2004

Pulse coupled neural networks with adaptive synapses for image segmentation.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2004, 2004

2003

CMOS image sensor with mixed-signal processor array.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

On-chip digital noise reduction for integrated CMOS Cameras.

[BibT_eX]

Markus Rullmann

Jens-Uwe Schluessler

Proceedings of the Visual Communications and Image Processing 2003, 2003

Optimized filter banks for the compression of subtraction angiographic images.

[BibT_eX]

[DOI]

Martin Franz

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

Comparison of accumulation units for analog realizations of a path searcher for a UMTS receiver.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Concept of Color Correction on Multi-Channel CMOS Sensors.

[BibT_eX]

[DOI]

Stephan Henker

Jens-Uwe Schluessler

Proceedings of the Seventh International Conference on Digital Image Computing: Techniques and Applications, 2003

Segmentation of Blood Vessels in Subtraction Angiographic Images.

[BibT_eX]

[DOI]

Martin Franz

Proceedings of the Seventh International Conference on Digital Image Computing: Techniques and Applications, 2003

2002

Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing, 2002

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 2002

CMOS image sensor with shared in-pixel amplifier and calibration facility.

[BibT_eX]

[DOI]

Achim Graupner

M. Tanzer

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

A vision device for image processing.

[BibT_eX]

Proceedings of the Signal and Image Processing (SIP 2001), 2001

Minimizing charge injection errors in high-precision, high-speed SC-circuits.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Robust Implementation and Statistical Modeling of a VI-Converter.

[BibT_eX]

[DOI]

Achim Graupner

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

Design of parallel preprocessing image sensors.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, 1999

A VLSI chip for wavelet image compression.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1996

An Architectural Study of a Massively Parallel Processor for Convolution-Type Operations in Complex Vision Tasks.

[BibT_eX]

[DOI]

Martin Franz

Proceedings of the Artificial Neural Networks, 1996

1977

Untersuchungen zur Gunn-Elektronik unter besonderer Berücksichtigung der numerischen Analyse.

[BibT_eX]

[DOI]

Rainer Götze