Johannes Schemmel
Orcid: 0000-0003-1440-4375Affiliations:
- University of Heidelberg, Germany
According to our database1,
Johannes Schemmel
authored at least 107 papers
between 1996 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on zbmath.org
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on orcid.org
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on d-nb.info
On csauthors.net:
Bibliography
2024
CoRR, 2024
2023
Simulation-based inference for model parameterization on analog neuromorphic hardware.
Neuromorph. Comput. Eng., December, 2023
From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system.
Neuromorph. Comput. Eng., September, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
A flexible column parallel successive-approximation ADC for hybrid neuromorphic computing.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Spiking Neural Network Linear Equalization: Experimental Demonstration of 2km 100Gb/s IM/DD PAM4 Optical Transmission.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
hxtorch.snn: Machine-learning-inspired Spiking Neural Network Modeling on BrainScaleS-2.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023
2022
The Heidelberg Spiking Data Sets for the Systematic Evaluation of Spiking Neural Networks.
IEEE Trans. Neural Networks Learn. Syst., 2022
Proc. Natl. Acad. Sci. USA, 2022
IEEE Open J. Circuits Syst., 2022
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Neural Networks, 2021
Nat. Mach. Intell., 2021
Towards Addressing Noise and Static Variations of Analog Computations Using Efficient Retraining.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
2020
Correction to: Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System.
J. Signal Process. Syst., 2020
J. Signal Process. Syst., 2020
Training spiking multi-layer networks with surrogate gradients on an analog neuromorphic substrate.
CoRR, 2020
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020
Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020
Live Demonstration: Versatile Emulation of Spiking Neural Networks on an Accelerated Neuromorphic Substrate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Versatile Emulation of Spiking Neural Networks on an Accelerated Neuromorphic Substrate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Neural Networks, 2019
The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks.
CoRR, 2019
Control of criticality and computation in spiking neuromorphic networks with plasticity.
CoRR, 2019
Brain-Inspired Hardware for Artificial Intelligence: Accelerated Learning in a Physical-Model Spiking Neural Network.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019
2018
An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Biomed. Circuits Syst., 2018
CoRR, 2018
Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster.
CoRR, 2018
2017
IEEE Trans. Biomed. Circuits Syst., 2017
Spiking neurons with short-term synaptic plasticity form superior generative networks.
CoRR, 2017
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.
CoRR, 2017
CoRR, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
An accelerated analog neuromorphic hardware system emulating NMDA- and calcium-based non-linear dendrites.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Robustness from structure: Inference with hierarchical spiking networks on analog neuromorphic hardware.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
CoRR, 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Probabilistic inference in discrete spaces can be implemented into networks of LIF neurons.
Frontiers Comput. Neurosci., 2015
2014
Proceedings of the Encyclopedia of Computational Neuroscience, 2014
Bridging the gap between software simulation and emulation on neuromorphic hardware: An investigation of causes, effects and compensation of network-level anomalies in a mixed-signal waferscale neuromorphic modeling platform.
CoRR, 2014
2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Towards biologically realistic multi-compartment neuron model emulation in analog VLSI.
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012
2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011
2010
Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.
Frontiers Comput. Neurosci., 2010
Proceedings of the Advances in Neural Information Processing Systems 23: 24th Annual Conference on Neural Information Processing Systems 2010. Proceedings of a meeting held 6-9 December 2010, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Live demonstration: Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.
Frontiers Neuroinformatics, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Realizing biological spiking network models in a configurable wafer-scale hardware system.
Proceedings of the International Joint Conference on Neural Networks, 2008
2007
Spike-Frequency Adapting Neural Ensembles: Beyond Mean Adaptation and Renewal Theories.
Neural Comput., 2007
Proceedings of the Computational and Ambient Intelligence, 2007
A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology.
Proceedings of the Computational and Ambient Intelligence, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Joint Conference on Neural Networks, 2006
Training convolutional networks of threshold neurons suited for low-power hardware implementation.
Proceedings of the International Joint Conference on Neural Networks, 2006
A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware.
Proceedings of the Artificial Neural Networks in Pattern Recognition, Second IAPR Workshop, 2006
A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
Operational Amplifiers: An Example for Multi-objective Optimization on an Analog Evolvable Hardware Platform.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2005
2004
Proceedings of the Advances in Neural Information Processing Systems 17 [Neural Information Processing Systems, 2004
Proceedings of the Genetic and Evolutionary Computation, 2004
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004
2003
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003
2002
Exploring The Parameter Space Of A Genetic Algorithm For Training An Analog Neural Network.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002
Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001
2000
Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000
1999
1996
Proceedings of the Mustererkennung 1996, 1996