Johannes Schemmel

According to our database1, Johannes Schemmel authored at least 52 papers between 1996 and 2019.

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Bibliography

2019
Brain-Inspired Hardware for Artificial Intelligence: Accelerated Learning in a Physical-Model Spiking Neural Network.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019

2018
An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture.
IEEE Trans. on Circuits and Systems, 2018

A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores.
IEEE Trans. Biomed. Circuits and Systems, 2018

2017
Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System.
IEEE Trans. Biomed. Circuits and Systems, 2017



An accelerated analog neuromorphic hardware system emulating NMDA- and calcium-based non-linear dendrites.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

Robustness from structure: Inference with hierarchical spiking networks on analog neuromorphic hardware.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

From LIF to AdEx neuron models: Accelerated analog 65 nm CMOS implementation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Probabilistic inference in discrete spaces can be implemented into networks of LIF neurons.
Front. Comput. Neurosci., 2015

2014
Neuromorphic Hardware, Large Scale.
Proceedings of the Encyclopedia of Computational Neuroscience, 2014

2013
A location-independent direct link neuromorphic interface.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Neuromorphic learning towards nano second precision.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

An analog dynamic memory array for neuromorphic hardware.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Towards biologically realistic multi-compartment neuron model emulation in analog VLSI.
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012

2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biological Cybernetics, 2011

2010
Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.
Front. Comput. Neurosci., 2010

A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model.
Proceedings of the Advances in Neural Information Processing Systems 23: 24th Annual Conference on Neural Information Processing Systems 2010. Proceedings of a meeting held 6-9 December 2010, 2010

A wafer-scale neuromorphic hardware system for large-scale neural modeling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Live demonstration: Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Establishing a novel modeling tool: a python-based interface for a neuromorphic hardware system.
Front. Neuroinform., 2009

A QoS network architecture to interconnect large-scale VLSI neural networks.
Proceedings of the International Joint Conference on Neural Networks, 2009

High-conductance states on a neuromorphic hardware system.
Proceedings of the International Joint Conference on Neural Networks, 2009

2008
Wafer-scale integration of analog neural networks.
Proceedings of the International Joint Conference on Neural Networks, 2008

Realizing biological spiking network models in a configurable wafer-scale hardware system.
Proceedings of the International Joint Conference on Neural Networks, 2008

2007
Spike-Frequency Adapting Neural Ensembles: Beyond Mean Adaptation and Renewal Theories.
Neural Computation, 2007

Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections.
Proceedings of the Computational and Ambient Intelligence, 2007

A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology.
Proceedings of the Computational and Ambient Intelligence, 2007

Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model.
Proceedings of the International Joint Conference on Neural Networks, 2006

Training convolutional networks of threshold neurons suited for low-power hardware implementation.
Proceedings of the International Joint Conference on Neural Networks, 2006

A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware.
Proceedings of the Artificial Neural Networks in Pattern Recognition, Second IAPR Workshop, 2006

A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Operational Amplifiers: An Example for Multi-objective Optimization on an Analog Evolvable Hardware Platform.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2005

2004
Edge of Chaos Computation in Mixed-Mode VLSI - A Hard Liquid.
Proceedings of the Advances in Neural Information Processing Systems 17 [Neural Information Processing Systems, 2004

On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA.
Proceedings of the Genetic and Evolutionary Computation, 2004

New Genetic Operators to Facilitate Understanding of Evolved Transistor Circuits.
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip.
Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

2003
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003

2002
Exploring The Parameter Space Of A Genetic Algorithm For Training An Analog Neural Network.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002

Towards an Artificial Neural Network Framework.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002

Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip.
Proceedings of the 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 2002

2001
An interactive tactile graphics display.
Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001

A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001

Initial Studies of a New VLSI Field Programmable Transistor Array.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2001

A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits.
Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001

2000
Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000

1999
An integrated analog network for image processing.
PhD thesis, 1999

1996
Entwicklung einer Kamera mit adaptiven Photorezeptoren in analoger CMOS-Technologie.
Proceedings of the Mustererkennung 1996, 1996


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