Andreas Grübl

Orcid: 0000-0002-3955-4815

According to our database1, Andreas Grübl authored at least 31 papers between 2006 and 2023.

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Bibliography

2023
From clean room to machine room: commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system.
Neuromorph. Comput. Eng., September, 2023

A flexible column parallel successive-approximation ADC for hybrid neuromorphic computing.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

2022
Surrogate gradients for analog neuromorphic computing.
Proc. Natl. Acad. Sci. USA, 2022

The operating system of the neuromorphic BrainScaleS-1 system.
Neurocomputing, 2022

Demonstrating BrainScaleS-2 Inter-Chip Pulse-Communication using EXTOLL.
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022

2021
BrainScaleS Large Scale Spike Communication using Extoll.
CoRR, 2021

2020
Correction to: Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System.
J. Signal Process. Syst., 2020

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System.
J. Signal Process. Syst., 2020

Training spiking multi-layer networks with surrogate gradients on an analog neuromorphic substrate.
CoRR, 2020

Inference with Artificial Neural Networks on Analog Neuromorphic Hardware.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020



2018
An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Mixed-Signal Structured AdEx Neuron for Accelerated Neuromorphic Cores.
IEEE Trans. Biomed. Circuits Syst., 2018

Demonstrating Advantages of Neuromorphic Computation: A Pilot Study.
CoRR, 2018

Generative models on accelerated neuromorphic hardware.
CoRR, 2018

Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster.
CoRR, 2018

2017
Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System.
IEEE Trans. Biomed. Circuits Syst., 2017

Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.
CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.
CoRR, 2017



Robustness from structure: Inference with hierarchical spiking networks on analog neuromorphic hardware.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2012
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011

2010
A VLSI Implementation of the Adaptive Exponential Integrate-and-Fire Neuron Model.
Proceedings of the Advances in Neural Information Processing Systems 23: 24th Annual Conference on Neural Information Processing Systems 2010. Proceedings of a meeting held 6-9 December 2010, 2010

A wafer-scale neuromorphic hardware system for large-scale neural modeling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2007
VLSI implementation of a spiking neural network.
PhD thesis, 2007

Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections.
Proceedings of the Computational and Ambient Intelligence, 2007

A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology.
Proceedings of the Computational and Ambient Intelligence, 2007

2006
Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model.
Proceedings of the International Joint Conference on Neural Networks, 2006


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