Stefan Scholze

According to our database1, Stefan Scholze authored at least 36 papers between 2010 and 2023.

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Bibliography

2023
A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.
Proceedings of the 20th International SoC Design Conference, 2023

A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021

Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.
J. Signal Process. Syst., 2020

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
Dynamic Power Management for Neuromorphic Many-Core Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2018
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017
Application-specific architectures for energy-efficient database query processing and optimization.
Microprocess. Microsystems, 2017

Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.
CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.
CoRR, 2017



Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017



2016
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
IEEE Trans. Biomed. Circuits Syst., 2016

A database accelerator for energy-efficient query processing and optimization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016


2015
An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.
CoRR, 2014

10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012
A 32 GBit/s communication SoC for a waferscale neuromorphic system.
Integr., 2012

A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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