Vincent Camus

Orcid: 0000-0003-4779-7742

According to our database1, Vincent Camus authored at least 15 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2019
Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits.
Proceedings of the 26th European Signal Processing Conference, 2018

2017
Design and Applications of Approximate Circuits by Gate-Level Pruning.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders.
Proceedings of the New Generation of CAS, 2017

Combining structural and timing errors in overclocked inexact speculative adders.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Design of energy-efficient discrete cosine transform using pruned arithmetic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Approximate 32-bit floating-point unit design with 53% power-area product reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A low-power <i>carry cut-back</i> approximate adder with fixed-point implementation and floating-point precision.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Energy-efficient digital design through inexact and approximate arithmetic circuits.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Automatic generation of inexact digital circuits by gate-level pruning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Energy-efficient inexact speculative adder with high performance and accuracy control.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015


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