Karol Desnos

According to our database1, Karol Desnos authored at least 42 papers between 2012 and 2019.

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Bibliography

2019
Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource Allocation.
ACM Trans. Embedded Comput. Syst., 2019

DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping.
Microprocess. Microsystems, 2019

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
Embedded Systems Letters, 2019

PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI.
IEEE Access, 2019

Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Accuracy Evaluation Based on Simulation for Finite Precision Systems Using Inferential Statistics.
Proceedings of the IEEE International Conference on Acoustics, 2019

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs.
Signal Processing Systems, 2018

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Algorithm-level approximation for fast (or not) embedded stereovision algorithm.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Delays and states in dataflow models of computation.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Energy-Efficient Actor Execution for SDF Application on Heterogeneous Architectures.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Model-Based Programming for Multi-processor Platforms with TTool/DIPLODOCUS and OMC.
Proceedings of the Model-Driven Engineering and Software Development, 2018

Stochastic Modeling to Accelerate Approximate Operators Simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures.
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018

A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits.
Proceedings of the 26th European Signal Processing Conference, 2018

Automatic instrumentation of dataflow applications using PAPI.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Smart search space reduction for approximate computing: A low energy HEVC encoder case study.
J. Syst. Archit., 2017

Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture.
J. Syst. Archit., 2017

Task-based execution of synchronous dataflow graphs for scalable multicore computing.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Relaxed subgraph execution model for the throughput evaluation of IBSDF graphs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Throughput evaluation of DSP applications based on hierarchical dataflow models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
Signal Processing Systems, 2016

On Memory Reuse Between Inputs and Outputs of Dataflow Actors.
ACM Trans. Embedded Comput. Syst., 2016

Off-Line DVFS Integration in MDE-Based Design Space Exploration Framework for MP2SoC Systems.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016

Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Distributed Memory Allocation Technique for Synchronous Dataflow Graphs.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application.
Signal Processing Systems, 2015

Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems.
Proceedings of the Software Engineering, 2015

Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Efficient multicore implementation of an advanced generator of discrete chaotic sequences.
Proceedings of the 9th International Conference for Internet Technology and Secured Transactions, 2014

MARTE to ΠSDF transformation for data-intensive applications analysis.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Scheduling of parallelized synchronous dataflow actors.
Proceedings of the 2013 International Symposium on System on Chip, 2013

2012
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012


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