Karol Desnos
Orcid: 0000-0003-1527-9668
According to our database1,
Karol Desnos
authored at least 57 papers
between 2012 and 2023.
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Bibliography
2023
Evaluation of Image Quality Assessment Metrics for Semantic Segmentation in a Machine-to-Machine Communication Scenario.
Proceedings of the 15th International Conference on Quality of Multimedia Experience, 2023
Proceedings of the 34th IEEE Annual International Symposium on Personal, 2023
Proceedings of the 25th IEEE International Workshop on Multimedia Signal Processing, 2023
Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity.
Proceedings of the 31st European Signal Processing Conference, 2023
Proceedings of the Design and Architecture for Signal and Image Processing, 2023
2022
SECURE-GEGELATI Always-On Intrusion Detection through GEGELATI Lightweight Tangled Program Graphs.
J. Signal Process. Syst., 2022
Ultra-Fast Machine Learning Inference through C Code Generation for Tangled Program Graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Video Coding for Machines: Large-Scale Evaluation of Deep Neural Networks Robustness to Compression Artifacts for Semantic Segmentation.
Proceedings of the 24th IEEE International Workshop on Multimedia Signal Processing, 2022
Proceedings of the Image Processing: Algorithms and Systems XX, 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
2021
Gegelati: Lightweight Artificial Intelligence through Generic and Evolvable Tangled Program Graphs.
Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021
2020
Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems.
J. Signal Process. Syst., 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time Constraints.
Proceedings of the 28th International Conference on Real Time Networks and Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource Allocation.
ACM Trans. Embed. Comput. Syst., 2019
DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping.
Microprocess. Microsystems, 2019
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators.
IEEE Embed. Syst. Lett., 2019
PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPI.
IEEE Access, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Accuracy Evaluation Based on Simulation for Finite Precision Systems Using Inferential Statistics.
Proceedings of the IEEE International Conference on Acoustics, 2019
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs.
J. Signal Process. Syst., 2018
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Proceedings of the Model-Driven Engineering and Software Development, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018
A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Cassis: Characterization with Adaptive Sample- Size Inferential Statistics Applied to Inexact Circuits.
Proceedings of the 26th European Signal Processing Conference, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Smart search space reduction for approximate computing: A low energy HEVC encoder case study.
J. Syst. Archit., 2017
Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture.
J. Syst. Archit., 2017
Task-based execution of synchronous dataflow graphs for scalable multicore computing.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
J. Signal Process. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
Off-Line DVFS Integration in MDE-Based Design Space Exploration Framework for MP2SoC Systems.
Proceedings of the 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2016
Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
2015
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application.
J. Signal Process. Syst., 2015
Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems.
Proceedings of the Software Engineering, 2015
Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
2014
Efficient multicore implementation of an advanced generator of discrete chaotic sequences.
Proceedings of the 9th International Conference for Internet Technology and Secured Transactions, 2014
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
2012
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012