Michael Gautschi

According to our database1, Michael Gautschi authored at least 19 papers between 2014 and 2018.

Collaborative distances:



In proceedings 
PhD thesis 


Online presence:

On csauthors.net:


A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Design of energy-efficient processing elements for near-threshold parallel computing.
PhD thesis, 2017

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster.
IEEE Micro, 2017

An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster.
IEEE J. Solid State Circuits, 2017

Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Approximate 32-bit floating-point unit design with 53% power-area product reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

High-efficiency logarithmic number unit design based on an improved cotransformation scheme.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

PULP: A parallel ultra low power platform for next generation IoT applications.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014