Vladimir M. Milovanovic

Orcid: 0000-0002-6787-4058

Affiliations:
  • University of Kragujevac, Faculty of Engineering, Serbia
  • Raytheon Vision Systems, Goleta, CA, USA
  • University of California at Berkeley, CA, USA
  • Vienna University of Technology, Institute of Electrodynamics, Microwave and Circuit Engineering, Austria
  • Delft University of Technology, The Netherlands (PhD 2010)


According to our database1, Vladimir M. Milovanovic authored at least 29 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Hardware Design Generator of High-Performance FIFO-Based Linear Insertion Streaming Sorters.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

Ethernet-Based In-System Testing and Utilization of IP Cores Implemented on FPGA Development Kits.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

On Hardware Implementations of Two-Dimensional Fast Fourier Transform for Radar Signal Processing.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

Optimization of Physics-Informed Neural Networks for Efficient Surrogate Modeling of Huxley's Muscle Model in Multi-Scale Finite Element Simulations.
Proceedings of the 23rd IEEE International Conference on Bioinformatics and Bioengineering, 2023

2022
A Deep Learning Model for Automatic Detection and Classification of Disc Herniation in Magnetic Resonance Images.
IEEE J. Biomed. Health Informatics, 2022

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.
IEEE J. Solid State Circuits, 2022

Associative Word Relations in Natural Language Processing.
Appl. Artif. Intell., 2022

2021
A Design Generator of Parametrizable and Runtime Configurable Constant False Alarm Rate Processors.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 130-nm 76-81-GHz SiGe TDM MIMO Radar Transmitter Array for Automotive Applications.
Proceedings of the 19th IEEE International Conference on Smart Technologies, 2021

A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

Machine Learning-based Image Processing in Support of Discus Hernia Diagnosis.
Proceedings of the 21st IEEE International Conference on Bioinformatics and Bioengineering, 2021

2020
Semiconductor Gas Sensors: Materials, Technology, Design, and Application.
Sensors, 2020

A comparison of classifiers in biomedical signal processing as a decision support system in disc hernia diagnosis.
Comput. Biol. Medicine, 2020

2019
A Customizable DDR3 SDRAM Controller Tailored for FPGA-Based Data Buffering Inside Real-Time Range-Doppler Radar Signal Processing Back Ends.
Proceedings of the IEEE EUROCON 2019, 2019

Natural Language Processing for Associative Word Predictions.
Proceedings of the IEEE EUROCON 2019, 2019

2018
A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
An FMCW fractional-N PLL-based synthesizer for integrated 79 GHz automotive radar sensors.
Proceedings of the IEEE EUROCON 2017 -17th International Conference on Smart Technologies, 2017

A low-voltage low-offset dual strong-arm latch comparator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Design of Energy- and Cost-Efficient Massive MIMO Arrays.
Proc. IEEE, 2016

On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2013
A fully differential CMOS self-biased two-stage preamplifier-latch threshold detection comparator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

On fully differential and complementary single-stage self-biased CMOS differential amplifiers.
Proceedings of Eurocon 2013, 2013

A 40 nm LP CMOS self-biased continuous-time comparator with sub-100ps delay at 1.1V & 1.2mW.
Proceedings of the ESSCIRC 2013, 2013

Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOS.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Analyses of single-stage complementary self-biased CMOS differential amplifiers.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

A fully complementary and fully differential self-biased asynchronous CMOS comparator.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
RF small signal avalanche for bipolar transistor circuit design: Characterization, modeling and repercussions.
Microelectron. Reliab., 2011

2009
Behavioural Biometrics Hardware Based on Bioinformatics Matching.
Proceedings of the Computational Intelligence in Security for Information Systems, 2009


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