Gabriel Caffarena

According to our database1, Gabriel Caffarena authored at least 39 papers between 2003 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2019
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs.
Integr., 2019

High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2016
Quantization Noise Power Estimation for Floating-Point DSP Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records.
Proceedings of the Bioinformatics and Biomedical Engineering, 2016

Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array.
Proceedings of the Bioinformatics and Biomedical Engineering, 2016

2015
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Iterative reconstruction for pet scanners with continuous scintillators.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2014
Comparing scientific performance among equals.
Scientometrics, 2014

Outlier detection for single particle analysis in Electron Microscopy.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

Hermite Polynomial Characterization of Heartbeats with Graphics Processing Units.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

2D and 3D Alignment for Electron Microscopy via Graphics Processing Units.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

FPGA Design of Delay-Based Digital Effects for Electric Guitar.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Self-Reconfigurable Constant Multiplier for FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2013

2012
A Discrete Model for Correlation Between Quantization Noises.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Quantization of VLSI digital signal processing systems.
EURASIP J. Adv. Signal Process., 2012

Image processing for Cellular tomography using soft X-rays.
Proceedings of the 9th IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2012

Many-core parallelization of fixed-point optimization of VLSI circuits through GPU devices.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2010
SQNR Estimation of Fixed-Point DSP Algorithms.
EURASIP J. Adv. Signal Process., 2010

Fast Fixed-Point Optimization of DSP Algorithms.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Architectural synthesis of DSP circuits under simultaneous error and time constraints.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

SQNR estimation of non-linear fixed-point algorithms.
Proceedings of the 18th European Signal Processing Conference, 2010

Precision-wise architectural synthesis of DSP circuits.
Proceedings of the 18th European Signal Processing Conference, 2010

2009
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs.
Int. J. Reconfigurable Comput., 2009

Behavioural Biometrics Hardware Based on Bioinformatics Matching.
Proceedings of the Computational Intelligence in Security for Information Systems, 2009

2008
Fast and accurate computation of the roundoff noise of linear time-invariant systems.
IET Circuits Devices Syst., 2008

Optimized Architectural Synthesis of Fixed-Point Datapaths.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Fpga Acceleration for DNA Sequence Alignment.
J. Circuits Syst. Comput., 2007

Switching Activity Models for Power Estimation in FPGA Multipliers.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

FPGA for pseudorandom generator cryptanalysis.
Microprocess. Microsystems, 2006

Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources.
Proceedings of the International Symposium on System-on-Chip, 2006

Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2004
High-speed systolic array for gene matching.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A Generator of High-Speed Floating-Point Modules.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Analysis of limit cycles by means of affine arithmetic computer-aided tests.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
Fast characterization of the noise bounds derived from coefficient and signal quantization.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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