Gabriel L. Nazar

Orcid: 0000-0001-7202-7139

Affiliations:
  • Federal University of Rio Grande do Sul (UFRGS), Institute of Informatics, Porto Alegre, Brazil (PhD 2013)


According to our database1, Gabriel L. Nazar authored at least 56 papers between 2010 and 2023.

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Bibliography

2023
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., December, 2023

Modular VNF Components Acceleration With FPGA Overlays.
IEEE Trans. Netw. Serv. Manag., March, 2023

GRASP-based High-Level Synthesis Design Space Exploration for FPGAs.
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023

Desafios para a Computação Energeticamente Eficiente.
Proceedings of the Escola de Computação PPGC/UFRGS 50 Anos: Transformando Desafios em Oportunidades Para o Futuro, 2023

2022
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Lightweight Dual Modular Redundancy through Approximate Computing.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

VNFAccel: An FPGA-based Platform for Modular VNF Components Acceleration.
Proceedings of the 17th IFIP/IEEE International Symposium on Integrated Network Management, 2021

2020
SoMMA: A software-managed memory architecture for multi-issue processors.
Microprocess. Microsystems, 2020

A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions.
IEEE Commun. Surv. Tutorials, 2020

Firefly: An Open-source Rocket-based Intermittent Framework.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

High-level synthesis of throughput-optimized and energy-efficient approximate designs.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
High-Level Synthesis of Approximate Designs under Real-Time Constraints.
ACM Trans. Embed. Comput. Syst., 2019

A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Cost-effective Resilient FPGA-based LDPC Decoder Architecture.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Repair of FPGA-Based Real-Time Systems With Variable Slacks.
ACM Trans. Design Autom. Electr. Syst., 2018

Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching.
J. Electron. Test., 2018

Precise evaluation of the fault sensitivity of OoO superscalar processors.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Exploring redundancy granularities to repair real-time FPGA-based systems.
Microprocess. Microsystems, 2017

An energy-efficient memory hierarchy for multi-issue processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Beyond Cross-Section: Spatio-Temporal Reliability Analysis.
ACM Trans. Embed. Comput. Syst., 2016

Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication.
ACM Trans. Embed. Comput. Syst., 2016

SBESC 2015 guest editors' introduction.
Des. Autom. Embed. Syst., 2016

Searching with a Corrupted Heuristic.
Proceedings of the Ninth Annual Symposium on Combinatorial Search, 2016

Improving performance in VLIW soft-core processors through software-controlled scratchpads.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A fault injection platform for FPGA-based communication systems.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Scalable memory architecture for soft-core processors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Low cost resilient regular expression matching on FPGAs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Low Cost Dynamic Scrubbing for Real-Time Systems.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Fine-Grained Fast Field-Programmable Gate Array Scrubbing.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Improving FPGA repair under real-time constraints.
Microelectron. Reliab., 2015

Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture.
Proceedings of the 16th Latin-American Test Symposium, 2015

2014
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems.
ACM Trans. Reconfigurable Technol. Syst., 2014

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Reducing embedded software radiation-induced failures through cache memories.
Proceedings of the 19th IEEE European Test Symposium, 2014

Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Reliable execution of statechart-generated correct embedded software under soft errors.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Accelerated FPGA repair through shifted scrubbing.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Scrubbing unit repositioning for fast error repair in FPGAs.
Proceedings of the International Conference on Compilers, 2013

2012
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Adapting communication for adaptable processors: A multi-axis reconfiguration approach.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Fast error detection through efficient use of hardwired resources in FPGAs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Fast single-FPGA fault injection platform.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Energy efficient pseudo-cache architecture through fine-grained reconfigurability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An Area Effective Parity-Based Fault Detection Technique for FPGAs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Implementation comparisons of the QR decomposition for MIMO detection.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010


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