Wei-Ming Lin

Orcid: 0000-0002-9350-6646

According to our database1, Wei-Ming Lin authored at least 76 papers between 1990 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Effective TLB thrashing: unveiling the true short reach of modern TLB designs.
Proceedings of the SAC '22: The 37th ACM/SIGAPP Symposium on Applied Computing, Virtual Event, April 25, 2022

2021
Exploiting Long-Term Temporal Cache Access Patterns for LRU Insertion Prioritization.
Parallel Process. Lett., 2021

Reinforcement learning-based register renaming policy for simultaneous multithreading CPUs.
Expert Syst. Appl., 2021

Branchboozle: a side-channel within a hidden pattern history table of modern branch prediction units.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

The Race-Timing Prototype.
Proceedings of the 18th International Conference on Privacy, Security and Trust, 2021

Deep Model Compression via Two-Stage Deep Reinforcement Learning.
Proceedings of the Machine Learning and Knowledge Discovery in Databases. Research Track, 2021

2020
Sensitivity of Pre-Contrast Multiphase versus Conventional Liver MRI in Diagnosing Hepatic Hemangioma.
J. Medical Imaging Health Informatics, 2020

An Asynchronous High-Performance Approximate Adder with Low-Cost Error Correction.
J. Inf. Sci. Eng., 2020

2019
Applied On-Chip Machine Learning for Dynamic Resource Control in Multithreaded Processors.
Parallel Process. Lett., 2019

Round Robin Thread Selection Optimization in Multithreaded Processors.
Parallel Process. Lett., 2019

Dynamic capping of rename registers for SMT processors.
J. Syst. Archit., 2019

Diagnostic Efficacy of Non-Contrast Liver Magnetic Resonance Imaging with Multiparametric Sequences in Hepatocellular Carcinoma.
J. Medical Imaging Health Informatics, 2019

2018
A controlled fetching technique for effective management of shared resources in SMT processors.
Microprocess. Microsystems, 2018

An integrated autonomous control mechanism to optimize sharing of multiple resources in Simultaneous Multi-Threading processors.
J. Syst. Archit., 2018

Real-time physical register file allocation with neural networks for simultaneous multi-threading processors.
Int. J. High Perform. Syst. Archit., 2018

2017
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance.
ACM Trans. Embed. Comput. Syst., 2017

Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

2016
Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors.
Microprocess. Microsystems, 2016

Improving Resource Utilization by Curbing Speculative Trace Progression in Simultaneous Multi-Threading CPUs.
J. Inf. Sci. Eng., 2016

2014
Autonomous control of issue queue utilization for simultaneous multi-threading processors.
Proceedings of the 2014 Spring Simulation Multiconference, 2014

A Real-Time Per-Thread IQ-Capping Technique for Simultaneous Multi-threading (SMT) Processors.
Proceedings of the 11th International Conference on Information Technology: New Generations, 2014

RMCC: Restful Mobile Cloud Computing Framework for Exploiting Adjacent Service-Based Mobile Cloudlets.
Proceedings of the IEEE 6th International Conference on Cloud Computing Technology and Science, 2014

2013
Recalling instructions from idling threads to maximize resource utilization for simultaneous multi-threading processors.
Comput. Electr. Eng., 2013

Static noise margin and power dissipation analysis of various SRAM topologies.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Capping Speculative Traces to Improve Performance in Simultaneous Multi-threading CPUs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors.
Comput. Electr. Eng., 2012

2011
Hybrid Key Duplication Hashing Techniques for IP Address Lookup.
Int. J. Commun. Netw. Syst. Sci., 2011

2010
Task Scheduling for Multiprocessor Systems with Autonomous Performance-Optimizing Control.
J. Inf. Sci. Eng., 2010

Advanced Hashing with Hybrid Key Duplication for IP Address Lookup.
Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010

2009
On designing fast nonuniformly distributed IP address lookup hashing algorithms.
IEEE/ACM Trans. Netw., 2009

A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Fast Random Variate Generation with Sorting-Based Rejection Techniques for Computer Simulation.
Int. J. Comput. Their Appl., 2009

Advanced Hash Algorithms with Key Bits Duplication for IP Address Lookup.
Proceedings of the Fifth International Conference on Networking and Services, 2009

2008
Performance modeling and analysis of correlated parallel computations.
Parallel Comput., 2008

AURED - Autonomous Random Early Detection for TCP Congestion Control.
Proceedings of the 3rd International Conference on Systems and Networks Communications, 2008

2007
Optimal XOR hashing for non-uniformly distributed address lookup in computer networks.
J. Netw. Comput. Appl., 2007

An Efficient Clustering-Based Task Scheduling Algorithm for Parallel Programs with Task Duplication.
J. Inf. Sci. Eng., 2007

2006
The Design of Efficient Hashing Techniques for IP Address Lookup.
Proceedings of the LCN 2006, 2006

Adaptive Hashing for IP Address Lookup in Computer Networks.
Proceedings of the 14th IEEE International Conference on Networks, 2006

Advanced hashing techniques for non-uniformly distributed IP address lookup.
Proceedings of the Third IASTED International Conference on Communications and Computer Networks, 2006

Advanced Hybrid Branch Predictors for High-Performance CPUs.
Proceedings of the 21st International Conference on Computers and Their Applications, 2006

2005
Improving Branch Prediction Performance with a Generalized Design for Dynamic Branch Predictors.
Informatica (Slovenia), 2005

Efficient Task Scheduling with Duplication for Bounded Number of Processors.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Job Scheduling with Real-Time Optimal Control.
Proceedings of the ISCA 14th International Conference on Intelligent and Adaptive Systems and Software Engineering, 2005

Improved Design and Implementation of Network Intrusion Detection System for Gigabit Network Traffic Using FPGA.
Proceedings of the ISCA 18th International Conference on Computer Applications in Industry and Engineering, 2005

Optimal XOR hashing for a linearly distributed address lookup in computer networks.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005

2004
A low-jitter mutual-correlated pulsewidth control loop circuit.
IEEE J. Solid State Circuits, 2004

Effective Branch Prediction through Caching of Aliasing Branches.
J. Inf. Sci. Eng., 2004

A Congestion-Relieving Mechanism for Wormhole-Routed Networks with Real-Time Injection Control.
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004

A Performance-Optimizing Scheduling Technique for Mesh-Connected Multicomputers Based on Real-Time Job Size Distribution.
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004

A Real-Time Ad Hoc Packet Matching Technique for Hardware-Based Network Intrusion Detection Systems.
Proceedings of the 19th International Conference on Computers and Their Applications, 2004

Task Scheduling Algorithm with Duplication for Distributed Computing.
Proceedings of the 17th International Conference on Computer Applications in Industry and Engineering, 2004

2003
A Bypass-Sensitive Blocking-Preventing Scheduling Technique for Mesh-Connected Multicomputers.
Proceedings of the High Performance Computing, 5th International Symposium, 2003

Improving Branch Prediction Performance by Removing Temporally Close Aliases.
Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003

Advanced Branch Prediction Based on a Generalized Predictor.
Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003

An Intelligent Congenstion-Relieving Mechanism for Wormhole-Routed Networks.
Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, 2003

2002
Loop Scheduling for Heterogeneous Computing Environment Based on Performance Prediction.
Scalable Comput. Pract. Exp., 2002

2000
Load-skewing task assignment to minimize communication conflicts on network of workstations.
Parallel Comput., 2000

Allocation-Time-Based Processor Allocation Schem for 2D Mesh Architecture.
J. Inf. Sci. Eng., 2000

1999
Task Scheduling on Bus-based Networks of Workstations.
Scalable Comput. Pract. Exp., 1999

Minimizing Communication Conflicts with Load-Skewing Task Assignment Techniques on Network of Workstations.
Informatica (Slovenia), 1999

1998
Look-Ahead Traffic Distribution in Wormhole-Routed Networks.
Proceedings of the Seventeenth Symposium on Reliable Distributed Systems, 1998

Allocation Time-Based Processor Allocation Scheme for 2D Mesh Architecture.
Proceedings of the International Conference on Parallel and Distributed Systems, 1998

Cost-efficient branch prediction hardwares.
Proceedings of the Computers and Their Applications (CATA-98), 1998

1997
Performance prediction based loop scheduling for heterogeneous computing environment.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

An efficient processor partitioning and thread mapping strategy for mesh-connected multiprocessor systems.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

Performance analysis for parallel solutions to generic search problems.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

1995
Probabilistic performance analysis for parallel search techniques.
Int. J. Parallel Program., 1995

1993
Stereo and Image Matching on Fixed Size Linear Arrays.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

Parallel Implementations of a Scalable Consistent Labeling Technique on Distributed Memory Multi-Processor Systems.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
Parallel implementation of neural networks.
J. VLSI Signal Process., 1992

1991
Algorithmic Mapping of Neural Network Models onto Parallel SIMD Machines.
IEEE Trans. Computers, 1991

Parallel algorithms and architectures for discrete relaxation technique.
Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1991

Parallel implementations of discrete relaxation technique on fixed size processor arrays.
Proceedings of the Application Specific Array Processors, 1991

1990
A Note on the Linear Transformation Method for Systolic Array Design.
IEEE Trans. Computers, 1990

Efficient Histogramming on Hypercube SIMD Machines.
Comput. Vis. Graph. Image Process., 1990


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