Huaxi Gu

According to our database1, Huaxi Gu authored at least 79 papers between 2005 and 2018.

Collaborative distances :
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A highly efficient dynamic router for application-oriented network on chip.
The Journal of Supercomputing, 2018

A joint optimization method for NoC topology generation.
The Journal of Supercomputing, 2018

An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip.
IEICE Transactions, 2018

2017
System-level modeling and performance evaluation of multistage optical network on chips (MONoCs).
Photonic Network Communications, 2017

Energy-Aware on-chip virtual machine placement for cloud-supported cyber-physical systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

3D network-on-chip design for embedded ubiquitous computing systems.
Journal of Systems Architecture - Embedded Systems Design, 2017

BARR: Congestion aware scheduling algorithm for Network-on-Chip router.
IEICE Electronic Express, 2017

BHyberCube: A MapReduce aware heterogeneous architecture for data center.
Comput. Sci. Inf. Syst., 2017

Testudo: A Low Latency and High-Efficient Memory-Centric Network Using Optical Interconnect.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

Thor: a server-level hybrid switching data center network with heterogeneous topologies.
Proceedings of the ACM Turing 50th Celebration Conference, 2017

2016
A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom.
IEEE Trans. VLSI Syst., 2016

A 3D multilayer optical network on chip based on mesh topology.
Photonic Network Communications, 2016

STorus: A new topology for optical network-on-chip.
Optical Switching and Networking, 2016

A non-blocking wavelength routing ONoC based on two-dimension bus architecture.
Microelectronics Journal, 2016

DRTL: A heat-balanced deadlock-free routing algorithm for 3D topology network-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Resource and load aware mapping algorithm for elastic optical network.
IEICE Electronic Express, 2016

Universal method for designing non-blocking multicast-supported on chip optical router.
IEICE Electronic Express, 2016

Dual priority congestion aware shared-resource Network-on-Chip architecture.
IEICE Electronic Express, 2016

Panzer: A 6 × 6 photonic router for optical network on chip.
IEICE Electronic Express, 2016

A crosstalk-aware wavelength assignment method for optical network-on-chip.
IEICE Electronic Express, 2016

RingCube - An incrementally scale-out optical interconnect for cloud computing data center.
Future Generation Comp. Syst., 2016

An adaptive partition-based multicast routing scheme for mesh-based Networks-on-Chip.
Computers & Electrical Engineering, 2016

Flow Driven Energy-Aware Routing Algorithm in Data Center Network.
Proceedings of the 17th International Conference on Parallel and Distributed Computing, 2016

Dynamic Ring-Based Multicast with Wavelength Reuse for Optical Network on Chips.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

A laser power management method for on-Chip photonic interconnect.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
A scalable AWG-based data center network for cloud computing.
Optical Switching and Networking, 2015

CSquare: A new kilo-core-oriented topology.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

WRH-ONoC: A wavelength-reused hierarchical architecture for optical Network on Chips.
Proceedings of the 2015 IEEE Conference on Computer Communications, 2015

2014
QBNoC: QoS-aware bufferless NoC architecture.
Microelectronics Journal, 2014

RONoC: A Reconfigurable Architecture for Application-Specific Optical Network-on-Chip.
IEICE Transactions, 2014

Design and implementation of a NoC router supporting multicast.
IEICE Electronic Express, 2014

On the design of a 3D optical interconnected memory system.
IEICE Electronic Express, 2014

H-cluster: a hybrid architecture for three-dimensional many-core chips.
IEICE Electronic Express, 2014

A 3D topology based-on partial overlapped clusters for NoC.
IEICE Electronic Express, 2014

A high image rejection SiGe low noise amplifier using passive notch filter.
IEICE Electronic Express, 2014

A Power Efficient and Compact Optical Interconnect for Network-on-Chip.
Computer Architecture Letters, 2014

2013
An energy- and buffer-aware fully adaptive routing algorithm for Network-on-Chip.
Microelectronics Journal, 2013

Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip.
IEICE Transactions, 2013

A CMOS OTA with extremely large DC open-loop voltage gain.
IEICE Electronic Express, 2013

A bufferless optical network-on-chip router.
IEICE Electronic Express, 2013

A low-jitter pulsewidth control loop with high supply noise rejection.
IEICE Electronic Express, 2013

A new stereo enhancement circuit for class-D amplifier.
IEICE Electronic Express, 2013

3D Networks-on-Chip mapping targeting minimum signal TSVs.
IEICE Electronic Express, 2013

Distributed Flow Scheduling in Energy-Aware Data Center Networks.
IEEE Communications Letters, 2013

A hybrid packet-circuit switched router for optical network on chip.
Computers & Electrical Engineering, 2013

A new optical interconnection network for data centers.
Proceedings of the 22nd Wireless and Optical Communication Conference, 2013

A New Approach to Multi-objective Virtual Machine Placement in Virtualized Data Center.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

Analyzing Packet-Level Routing in Data Centers.
Proceedings of the IEEE 11th International Conference on Dependable, 2013

2012
Ultra Linear Modulator with High Output RF Gain Using a 1×2 MMI Coupler.
IEICE Transactions, 2012

Thermal and competition aware mapping for 3D network-on-chip.
IEICE Electronic Express, 2012

A multi-wavelength communication strategy for 2D-mesh Network-on-Chip.
IEICE Electronic Express, 2012

A virtual hierarchical optical mesh based data center network.
IEICE Electronic Express, 2012

A fast-locking low-jitter pulsewidth control loop for high-speed pipelined ADC.
IEICE Electronic Express, 2012

Cluster mesh: a topology for three-dimensional network-on-chip.
IEICE Electronic Express, 2012

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference.
IEICE Electronic Express, 2012

A crosstalk aware routing algorithm for Benes ONoC.
IEICE Electronic Express, 2012

DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip.
Computers & Electrical Engineering, 2012

A Multi-objective Mapping Strategy for Application Specific Emesh Network-on-Chip (NoC).
Proceedings of the Advances in Swarm Intelligence - Third International Conference, 2012

A New Two-Layer Topology for Data Center Network.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

2011
Intelligent Bees for QoS Routing in Networks-on-Chip
CoRR, 2011

An improved distributed routing algorithm for Benes based optical NoC
CoRR, 2011

An Efficient Bee Behavior-Based Multi-function Routing Algorithm for Network-on-Chip.
Proceedings of the Advances in Swarm Intelligence - Second International Conference, 2011

Artificial Bee Colony Based Mapping for Application Specific Network-on-Chip Design.
Proceedings of the Advances in Swarm Intelligence - Second International Conference, 2011

2010
A new distributed congestion control mechanism for networks on chip.
Telecommunication Systems, 2010

Fault tolerant routing algorithm based on the artificial potential field model in Network-on-Chip.
Applied Mathematics and Computation, 2010

2009
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A novel optical mesh network-on-chip for gigascale systems-on-chip.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Enhanced fault tolerant routing algorithms using a concept of "balanced ring".
Journal of Systems Architecture, 2007

A New Inner Congestion Control Mechanism in Terabit Routers.
Proceedings of the 8th ACIS International Conference on Software Engineering, 2007

RTOIN: a new scalable optical interconnection network.
Proceedings of the 2nf International Conference on Scalable Information Systems, 2007

A New Load Balanced Routing Algorithm for Torus Networks.
Proceedings of the Combinatorics, 2007

rHALB: A New Load-Balanced Routing Algorithm for k-ary n-cube Networks.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

2006
Routing in Hexagonal Networks under a Corner-Based Addressing Scheme.
IEICE Transactions, 2006

X-Torus: A Variation of Torus Topology with Lower Diameter and Larger Bisection Width.
Proceedings of the Computational Science and Its Applications, 2006

2005
A New Routing Method to Tolerate both Convex and Concave.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Choice of Inner Switching Mechanisms in Terabit Router.
Proceedings of the Networking, 2005

Building a Terabit Router with XD Networks.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005


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