Zuodong Zhang

Orcid: 0000-0002-8496-6114

According to our database1, Zuodong Zhang authored at least 32 papers between 2017 and 2026.

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Timeline

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Bibliography

2026
Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators.
CoRR, April, 2026

LEGALM 2.0: A Versatile Augmented Lagrangian Method-Based Methodology for Mixed-Cell-Height Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

RegPlace: Regularity-Aware Placement for Full-System DNN Accelerator Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2026

The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization.
CoRR, January, 2026

HeteroLatch: A CPU-GPU Heterogeneous Latch-Aware Timing Analysis Engine.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
GAP-LA: GPU-Accelerated Performance-Driven Layer Assignment.
CoRR, July, 2025

LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method.
Proceedings of the 2025 International Symposium on Physical Design, 2025

GPU Acceleration for Versatile Buffer Insertion.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

DiffCCD: Differentiable Concurrent Clock and Data Optimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

RUPlace: Optimizing Routability via Unified Placement and Routing Formulation.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR, 2024

Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Circuit Reliability Comparison Between Stochastic Computing and Binary Computing.
IEEE Trans. Circuits Syst., 2020

Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
A Parallel Bitstream Generator for Stochastic Computing.
CoRR, 2019

Modulation and Demodulation of Digital Frequency Shift Keying System Based on Spin Torque Nano Oscillator with Voltage Controlled Magnetic Anisotropy Effect.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.
Proceedings of the International Conference on IC Design and Technology, 2019

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2017
Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017


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