Wenjing Rao

Natasha Devroye

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

APUF Production Line Faults: Uniqueness and Testing.

[BibT_eX]

[DOI]

Yeqi Wei

Natasha Devroye

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

APUF Faults: Impact, Testing, and Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2020

The existence of universally agreed fairest semi-matchings in any given bipartite graph.

[BibT_eX]

[DOI]

Jian Xu

Theor. Comput. Sci., 2020

2018

Repairability Enhancement of Scalable Systems with Locally Shared Spares.

[BibT_eX]

[DOI]

CoRR, 2018

Hardware Obfuscation Using Strong PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A General Design Framework for Sparse Parallel Prefix Adders.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A local reconfiguration based scalable fault tolerant many-processor array.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

An STT-MRAM based strong PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A general approach for highly defect tolerant Parallel Prefix Adder design.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

IC Piracy prevention via Design Withholding and Entanglement.

[BibT_eX]

[DOI]

Kai Da Zhao

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A standard cell approach for MagnetoElastic NML circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013

Decentralized self-balancing systems.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Constructing spare sharing networks for reliability enhancement of scalable systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Spare sharing network enhancement for scalable systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Defect-tolerant logic hardening for crossbar-based nanosystems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge.

[BibT_eX]

[DOI]

Computer, 2011

Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

On mismatch number distribution of nanocrossbar logic mapping.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

2009

Logic Mapping in Crossbar-Based Nanoarchitectures.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Towards reliable nanoelectronic systems.

[BibT_eX]

[DOI]

PhD thesis, 2008

Locality aware redundancy allocation in nanoelectronic systems.

[BibT_eX]

[DOI]

Keith Marzullo

Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Selective Hardening of NanoPLA Circuits.

[BibT_eX]

[DOI]

Ilia Polian

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Towards fault tolerant parallel prefix adders in nanoelectronic systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Towards Nanoelectronics Processor Architectures.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.

[BibT_eX]

[DOI]

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Topology aware mapping of logic functions onto nanowire-based crossbar architectures.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Fault tolerant nanoelectronic processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Frugal linear network-based test decompression for drastic test cost reductions.

[BibT_eX]

[DOI]

George Su

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Virtual Compression through Test Vector Stitching for Scan Based Designs.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Test application time and volume compression through seed overlapping.

[BibT_eX]

[DOI]

Ismet Bayraktaroglu