William John Bainbridge

According to our database1, William John Bainbridge authored at least 10 papers between 1998 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Area efficient asynchronous SDM routers using 2-stage Clos switches.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2009
Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2004
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.
Proceedings of the 2004 Design, 2004

2003
SPA - a secure Amulet core for smartcard applications.
Microprocess. Microsystems, 2003

Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
SPA - A Synthesisable Amulet Core for Smartcard pplications.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
MARBLE: an asynchronous on-chip macrocell bus.
Microprocess. Microsystems, 2000

AMULET3i - An Asynchronous System-on-Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998
Asynchronous Macrocell Interconnect using MARBLE.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998


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