Luis A. Plana
Orcid: 0000-0002-6113-3929
According to our database1,
Luis A. Plana
authored at least 76 papers
between 1996 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress.
Proceedings of the High Performance Computing, 2023
A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
2020
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.
Simul. Model. Pract. Theory, 2020
IEEE Access, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst., 2018
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016
2015
Analysis of FPGA and software approaches to simulate unconventional computer architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
2014
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2013, 2013
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
J. Parallel Distributed Comput., 2012
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
Int. J. Parallel Program., 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A hierachical configuration system for a massively parallel neural hardware platform.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput., 2011
Neural Networks, 2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the Neural Information Processing - 18th International Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.
Fundam. Informaticae, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
IEEE Des. Test Comput., 2007
Proceedings of the 2007 International Conference on Compilers, 2007
2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
Proceedings of the 2004 Design, 2004
2003
Microprocess. Microsystems, 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996