Jim D. Garside

Orcid: 0000-0001-8812-4742

Affiliations:
  • University of Manchester, UK


According to our database1, Jim D. Garside authored at least 80 papers between 1992 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021

2020
Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks.
Simul. Model. Pract. Theory, 2020

spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.
IEEE Access, 2020

2019
Dynamic Power Management for Neuromorphic Many-Core Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst., 2018

Resource Elastic Virtualization for FPGAs Using OpenCL.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2017

HyperMAMBO-X64: Using Virtualization to Support High-Performance Transparent Binary Translation.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Low overhead dynamic binary translation on ARM.
Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2017


Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Optimizing Indirect Branches in Dynamic Binary Translators.
ACM Trans. Archit. Code Optim., 2016

DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs.
Proceedings of the Second International Symposium on Memory Systems, 2016

HAPPY: Hybrid Address-based Page Policy in DRAMs.
Proceedings of the Second International Symposium on Memory Systems, 2016

On-chip order-exploiting routing table minimization for a multicast supercomputer network.
Proceedings of the 17th IEEE International Conference on High Performance Switching and Routing, 2016

Parallel Hardware Merge Sorter.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Automatic Clock: A Promising Approach toward GALSification.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

Asynchronous Dataflow De-Elastisation for Efficient Heterogeneous Synthesis.
Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016

2015
SpiNNaker - Programming Model.
IEEE Trans. Computers, 2015

Analysis of FPGA and software approaches to simulate unconventional computer architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

De-elastisation: from asynchronous dataflows to synchronous circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes.
Microprocess. Microsystems, 2014

Automatic data path extraction in large-scale register-transfer level designs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Overview of the SpiNNaker System Architecture.
IEEE Trans. Computers, 2013

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Automatic Controller Detection for Large Scale RTL Designs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Scalable communications for a million-core neural processing architecture.
J. Parallel Distributed Comput., 2012

Area efficient asynchronous SDM routers using 2-stage Clos switches.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2011

2009
The Amulet chips: Architectural development for asynchronous microprocessors.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A Programmable Adaptive Router for a GALS Parallel System.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

Fault Tolerant Delay Insensitive Inter-chip Communication.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
An adaptive bloom filter cache partitioning scheme for multicore architectures.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

2007
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Modernization of teaching in embedded systems design - an international collaborative project.
IEEE Trans. Educ., 2006

2005
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Low-Power Processor Architecture Optimized forWireless Devices.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
A CAM with mixed serial-parallel comparison for use in low energy caches.
IEEE Trans. Very Large Scale Integr. Syst., 2004

An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
SPA - a secure Amulet core for smartcard applications.
Microprocess. Microsystems, 2003

An asynchronous copy-back cache architecture.
Microprocess. Microsystems, 2003

Adaptive Pipeline Structures fo Speculation Control.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Logic Design of Asynchronous Circuits (Tutorial Abstract).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An adaptive serial-parallel CAM architecture for low-power cache blocks.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Adaptive Pipeline Depth Control for Processor Power-Management.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

An Asynchronous Victim Cache.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

SPA - A Synthesisable Amulet Core for Smartcard pplications.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Power Management in the Amulet Microprocessors.
IEEE Des. Test Comput., 2001

A Practical Comparison of Asynchronous Design Styles.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

AMULET3i Cache Architecture.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
AMULET3: A 100 MIPS Asynchronous Embedded Processor.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

AMULET3i - An Asynchronous System-on-Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
AMULET2e: an asynchronous embedded controller.
Proc. IEEE, 1999

Memory Faults in Asynchronous Microprocessors.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

AMULET3 Revealed.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Asynchronous Embedded Control.
Integr. Comput. Aided Eng., 1998

AMULET3: a high-performance self-timed ARM microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
AMULET1: A Asynchronous ARM Microprocessor.
IEEE Trans. Computers, 1997

A Result Forwarding Mechanism for Asynchronous Pipelined Systems.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

AMULET2e: An Asynchronous Embedded Controller.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
The AMULET2e cache system.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1994
The Design and Evaluation of an Asynchronous Microprocessor.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

AMULET1: A Micropipelined ARM.
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994

1993
A micropipelined ARM.
Proceedings of the VLSI 93, 1993

A CMOS VLSI Implementation of an Asynchronous ALU.
Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993

1992
Register Locking in an Asynchronous Microprocessor.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992


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