William B. Toms

According to our database, William B. Toms authored at least 16 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

DiAD - Distributed Acceleration for Datacenter FPGAs.

Joshua Lant, Emmanouil Skordalakis, Kyriakos Paraskevas, William B. Toms, Mikel Luján, John Goodacre

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022

Energy-Efficient Encoding for High-Speed Serial Interfaces.

Eleni Maragkoudaki, William B. Toms, Vasilis F. Pavlidis

IEEE Trans. Very Large Scale Integr. Syst., 2022

2021

Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating.

William B. Toms, John Goodacre, Mikel Luján

Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2017

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation.

John Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms, Mikel Luján

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling.

Yaman Cakmaki, Will Toms, Javier Navaridas, Mikel Luján

IEEE Comput. Archit. Lett., 2016

2015

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems.

Behram Khan, Daniel Goodman, Salman Khan, Will Toms, Paolo Faraboschi, Mikel Luján, Ian Watson

J. Supercomput., 2015

2014

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA.

Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic.

P. Balasubramanian, David A. Edwards, William B. Toms

J. Circuits Syst. Comput., 2013

2012

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.

P. Balasubramanian, David A. Edwards, William B. Toms

VLSI Design, 2012

2011

Indicating combinational logic decomposition.

William B. Toms, David A. Edwards

IET Comput. Digit. Tech., 2011

2010

M-of-N Code Decomposition for Indicating Combinational Logic.

William B. Toms, David A. Edwards

Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths.

William B. Toms, David A. Edwards

Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

2009

Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks.

William B. Toms, Doug A. Edwards

Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2006

Synthesising Heterogeneously Encoded Systems.

William B. Toms, David A. Edwards, Andrew Bardsley

Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005

Efficient synthesis of speed-independent combinational logic circuits.

William B. Toms, David A. Edwards

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003

Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes.

W. J. Bainbridge, William B. Toms, David A. Edwards, Stephen B. Furber

Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003