Steve Temple

According to our database1, Steve Temple authored at least 36 papers between 1986 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.
IEEE Access, 2020

2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017


Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
SpiNNaker - Programming Model.
IEEE Trans. Computers, 2015

SpiNNaker: Enhanced multicast routing.
Parallel Comput., 2015

2014
The SpiNNaker Project.
Proc. IEEE, 2014

On generating multicast routes for SpiNNaker.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Overview of the SpiNNaker System Architecture.
IEEE Trans. Computers, 2013

SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013

SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013

A location-independent direct link neuromorphic interface.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2012
Scalable communications for a million-core neural processing architecture.
J. Parallel Distributed Comput., 2012

SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput., 2011

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2011

2010
Modeling Spiking Neural Networks on SpiNNaker.
Comput. Sci. Eng., 2010

Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system.
Proceedings of the International Joint Conference on Neural Networks, 2010

2009
The Amulet chips: Architectural development for asynchronous microprocessors.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Neural Systems Engineering.
Proceedings of the Computational Intelligence: A Compendium, 2008

2007
A GALS Infrastructure for a Massively Parallel Multiprocessor.
IEEE Des. Test Comput., 2007

2006
On-chip and inter-chip networks for modeling large-scale neural systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004
Sparse distributed memory using <i>N</i>-of-<i>M</i> codes.
Neural Networks, 2004

2003
SPA - a secure Amulet core for smartcard applications.
Microprocess. Microsystems, 2003

2002
SPA - A Synthesisable Amulet Core for Smartcard pplications.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Power Management in the Amulet Microprocessors.
IEEE Des. Test Comput., 2001

2000
AMULET3i - An Asynchronous System-on-Chip.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998
Asynchronous Embedded Control.
Integr. Comput. Aided Eng., 1998

1997
AMULET1: A Asynchronous ARM Microprocessor.
IEEE Trans. Computers, 1997

AMULET2e: An Asynchronous Embedded Controller.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
The AMULET2e cache system.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1994
The Design and Evaluation of an Asynchronous Microprocessor.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1986
Local area network design.
International computer science series, Addison-Wesley, ISBN: 978-0-201-13797-2, 1986


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